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Searched refs:inst_idx (Results 1 – 8 of 8) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dvcn_v4_0.c458 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), in vcn_v4_0_mc_resume_dpg_mode()
762 int inst_idx, uint8_t indirect) in vcn_v4_0_disable_clock_gating_dpg_mode() argument
881 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_enable_ras()
886 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_enable_ras()
916 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v4_0_start_dpg_mode()
944 VCN, inst_idx, regUVD_MPC_CNTL), in vcn_v4_0_start_dpg_mode()
948 VCN, inst_idx, regUVD_MPC_SET_MUXA0), in vcn_v4_0_start_dpg_mode()
955 VCN, inst_idx, regUVD_MPC_SET_MUXB0), in vcn_v4_0_start_dpg_mode()
962 VCN, inst_idx, regUVD_MPC_SET_MUX), in vcn_v4_0_start_dpg_mode()
983 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v4_0_start_dpg_mode()
[all …]
A Dvcn_v3_0.c530 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_mc_resume_dpg_mode()
584 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v3_0_mc_resume_dpg_mode()
956 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v3_0_start_dpg_mode()
985 VCN, inst_idx, mmUVD_MPC_CNTL), in vcn_v3_0_start_dpg_mode()
989 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), in vcn_v3_0_start_dpg_mode()
996 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), in vcn_v3_0_start_dpg_mode()
1003 VCN, inst_idx, mmUVD_MPC_SET_MUX), in vcn_v3_0_start_dpg_mode()
1030 VCN, inst_idx, mmUVD_MASTINT_EN), in vcn_v3_0_start_dpg_mode()
1038 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, in vcn_v3_0_start_dpg_mode()
1042 ring = &adev->vcn.inst[inst_idx].ring_dec; in vcn_v3_0_start_dpg_mode()
[all …]
A Dvcn_v2_5.c64 int inst_idx, struct dpg_pause_state *new_state);
786 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
791 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
796 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
817 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v2_5_start_dpg_mode()
880 vcn_v2_6_enable_ras(adev, inst_idx, indirect); in vcn_v2_5_start_dpg_mode()
897 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, in vcn_v2_5_start_dpg_mode()
901 ring = &adev->vcn.inst[inst_idx].ring_dec; in vcn_v2_5_start_dpg_mode()
933 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v2_5_start_dpg_mode()
936 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start_dpg_mode()
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A Damdgpu_vcn.h82 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
88 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
93 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
94 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
95 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
102 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \ argument
137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
141 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
148 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
[all …]
A Dvcn_v1_0.c54 int inst_idx, struct dpg_pause_state *new_state);
1210 int inst_idx, struct dpg_pause_state *new_state) in vcn_v1_0_pause_dpg_mode() argument
1218 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v1_0_pause_dpg_mode()
1220 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1221 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1270 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v1_0_pause_dpg_mode()
1274 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { in vcn_v1_0_pause_dpg_mode()
1276 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1277 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1331 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; in vcn_v1_0_pause_dpg_mode()
A Dvcn_v2_0.c62 int inst_idx, struct dpg_pause_state *new_state);
1202 int inst_idx, struct dpg_pause_state *new_state) in vcn_v2_0_pause_dpg_mode() argument
1209 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_0_pause_dpg_mode()
1211 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_0_pause_dpg_mode()
1272 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_0_pause_dpg_mode()
A Damdgpu_psp.h460 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
A Damdgpu_psp.c2831 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, in psp_update_vcn_sram() argument
2836 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : in psp_update_vcn_sram()

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