| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| A D | link_dp_capability.c | 433 switch (lane_count) { in reduce_lane_count()
469 switch (lane_count) { in increase_lane_count()
522 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && in decide_fallback_link_setting_max_bw_policy()
532 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count || in decide_fallback_link_setting_max_bw_policy()
550 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count; in decide_fallback_link_setting_max_bw_policy()
594 cur->lane_count = reduce_lane_count(cur->lane_count); in decide_fallback_link_setting()
604 cur->lane_count = reduce_lane_count(cur->lane_count); in decide_fallback_link_setting()
613 cur->lane_count = max->lane_count; in decide_fallback_link_setting()
629 cur->lane_count = max->lane_count; in decide_fallback_link_setting()
849 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) { in decide_edp_link_settings_with_dsc()
[all …]
|
| A D | link_dp_training_fixed_vs_pe_retimer.c | 96 uint8_t lane_count) in dp_fixed_vs_pe_set_retimer_lane_settings() argument
111 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
294 lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence()
333 lt_settings->link_settings.lane_count, in dp_perform_fixed_vs_pe_training_sequence()
346 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence() local
403 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence()
447 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dp_perform_fixed_vs_pe_training_sequence()
488 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence() local
508 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence()
559 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dp_perform_fixed_vs_pe_training_sequence()
[all …]
|
| A D | link_dp_training_8b_10b.c | 103 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
163 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_clock_recovery_sequence() local
228 if (dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_8b_10b_clock_recovery_sequence()
265 return dp_get_cr_failure(lane_count, dpcd_lane_status); in perform_8b_10b_clock_recovery_sequence()
277 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_channel_equalization_sequence() local
332 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_8b_10b_channel_equalization_sequence()
338 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
339 dp_is_symbol_locked(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
|
| A D | link_dp_training_dpia.c | 299 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_non_transparent() local
404 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_non_transparent()
409 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_non_transparent()
468 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_transparent() local
511 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_transparent()
622 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_non_transparent() local
716 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_non_transparent()
721 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in dpia_training_eq_non_transparent()
770 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_transparent() local
803 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_transparent()
[all …]
|
| A D | link_dp_training.c | 167 lt_settings->link_settings.lane_count, in dp_log_training_result()
452 (uint32_t)(lt_settings->link_settings.lane_count); in dp_is_max_vs_reached()
1035 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
1081 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1091 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1116 link_training_setting->link_settings.lane_count); in dpcd_set_lane_settings()
1335 enum dc_lane_count lane_count = in perform_post_lt_adj_req_sequence() local
1336 lt_settings->link_settings.lane_count; in perform_post_lt_adj_req_sequence()
1561 cur_link_settings.lane_count); in perform_link_training_with_retries()
1613 link->verified_link_cap.lane_count = link->cur_link_settings.lane_count; in perform_link_training_with_retries()
[all …]
|
| A D | link_dp_irq_handler.c | 56 if (link->cur_link_settings.lane_count == 0) in dc_link_check_link_loss_status()
62 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dc_link_check_link_loss_status()
192 pipes[i]->link_config.dp_link_settings.lane_count = in dc_link_dp_handle_link_loss()
193 link->verified_link_cap.lane_count; in dc_link_dp_handle_link_loss()
258 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || in dc_link_dp_allow_hpd_rx_irq()
|
| A D | link_dp_training_fixed_vs_pe_retimer.h | 39 uint8_t lane_count);
|
| /linux-6.3-rc2/drivers/gpu/drm/bridge/analogix/ |
| A D | analogix_dp_core.c | 264 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
321 lane_count); in analogix_dp_link_start()
350 int lane_count) in analogix_dp_channel_eq_ok() argument
446 int lane, lane_count; in analogix_dp_get_adjust_training_lane() local
449 lane_count = dp->link_train.lane_count; in analogix_dp_get_adjust_training_lane()
469 int lane, lane_count, retval; in analogix_dp_process_clock_recovery() local
475 lane_count = dp->link_train.lane_count; in analogix_dp_process_clock_recovery()
541 int lane, lane_count, retval; in analogix_dp_process_equalizer_training() local
547 lane_count = dp->link_train.lane_count; in analogix_dp_process_equalizer_training()
585 dp->link_train.lane_count); in analogix_dp_process_equalizer_training()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/msm/dp/ |
| A D | dp_panel.h | 91 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
93 return (lane_count == 1 || in is_lane_count_valid()
94 lane_count == 2 || in is_lane_count_valid()
95 lane_count == 4); in is_lane_count_valid()
|
| /linux-6.3-rc2/drivers/gpu/drm/i915/display/ |
| A D | intel_dp_link_training.c | 322 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
421 crtc_state->lane_count, in intel_dp_get_adjust_train()
429 crtc_state->lane_count, in intel_dp_get_adjust_train()
464 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
541 crtc_state->lane_count, in intel_dp_set_signal_levels()
549 crtc_state->lane_count, in intel_dp_set_signal_levels()
584 return ret == crtc_state->lane_count; in intel_dp_update_link_train()
692 link_config[1] = crtc_state->lane_count; in intel_dp_prepare_link_train()
972 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
983 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
[all …]
|
| A D | intel_dp.h | 42 int link_rate, int lane_count);
44 int link_rate, u8 lane_count);
107 u32 link_clock, u32 lane_count,
118 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
120 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
|
| A D | intel_dpio_phy.c | 594 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask()
602 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask()
724 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
737 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
790 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
816 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
833 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
899 if (crtc_state->lane_count > 2) { in chv_phy_pre_pll_enable()
943 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
952 if (crtc_state->lane_count == 1) in chv_phy_pre_encoder_enable()
[all …]
|
| A D | vlv_dsi.c | 56 8 * 100), lane_count); in txbyteclkhs()
63 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1109 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1161 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1215 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1217 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1219 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1311 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings() local
1334 hactive = txbyteclkhs(hactive, bpp, lane_count, in set_dsi_timings()
1337 hsync = txbyteclkhs(hsync, bpp, lane_count, in set_dsi_timings()
[all …]
|
| A D | intel_combo_phy.c | 267 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument
275 switch (lane_count) { in intel_combo_phy_power_up_lanes()
286 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
293 switch (lane_count) { in intel_combo_phy_power_up_lanes()
303 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
|
| A D | vlv_dsi_pll.c | 48 int lane_count) in dsi_clk_from_pclk() argument
55 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
168 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_pclk()
183 intel_dsi->lane_count); in vlv_dsi_pll_compute()
352 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_pclk()
491 intel_dsi->lane_count); in bxt_dsi_pll_compute()
|
| A D | intel_dp.c | 568 u8 lane_count) in intel_dp_link_params_valid() argument
579 if (lane_count == 0 || in intel_dp_link_params_valid()
588 u8 lane_count) in intel_dp_can_link_train_fallback_for_edp() argument
632 lane_count)) { in intel_dp_get_link_train_fallback_values()
639 } else if (lane_count > 1) { in intel_dp_get_link_train_fallback_values()
643 lane_count >> 1)) { in intel_dp_get_link_train_fallback_values()
1364 lane_count <<= 1) { in intel_dp_compute_link_config_wide()
1366 lane_count); in intel_dp_compute_link_config_wide()
1369 pipe_config->lane_count = lane_count; in intel_dp_compute_link_config_wide()
2184 intel_dp->lane_count = lane_count; in intel_dp_set_link_params()
[all …]
|
| A D | intel_crtc_state_dump.c | 29 const char *id, unsigned int lane_count, in intel_dump_m_n_config() argument
36 id, lane_count, in intel_dump_m_n_config()
214 pipe_config->lane_count, in intel_crtc_state_dump()
217 pipe_config->lane_count, in intel_crtc_state_dump()
|
| A D | intel_combo_phy.h | 18 int lane_count, bool lane_reversal);
|
| /linux-6.3-rc2/drivers/gpu/drm/gma500/ |
| A D | cdv_intel_dp.c | 262 uint8_t lane_count; member
898 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
911 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
917 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
991 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1008 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
1011 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
1055 switch (intel_dp->lane_count) { in cdv_intel_dp_mode_set()
1388 intel_dp->lane_count); in cdv_intel_dplink_set_level()
1390 if (ret != intel_dp->lane_count) { in cdv_intel_dplink_set_level()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/bridge/ |
| A D | parade-ps8622.c | 55 u32 lane_count; member
185 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
491 &ps8622->lane_count)) { in ps8622_probe()
492 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
493 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
496 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
|
| A D | ite-it6505.c | 428 u8 lane_count; member
803 switch (it6505->lane_count) { in it6505_lane_termination_on()
815 switch (it6505->lane_count) { in it6505_lane_termination_on()
1467 it6505->lane_count); in it6505_parse_link_capabilities()
1468 it6505->lane_count = min_t(int, it6505->lane_count, in it6505_parse_link_capabilities()
1543 (it6505->lane_count - 1) << 1); in it6505_lane_count_setup()
1560 it6505->lane_count, in it6505_link_training_setup()
1601 values[1] = it6505->lane_count; in it6505_drm_dp_link_configure()
1624 u8 lane_count) in it6505_check_max_voltage_swing_reached() argument
1628 for (i = 0; i < lane_count; i++) { in it6505_check_max_voltage_swing_reached()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_dio_link_encoder.c | 478 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_output()
525 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_mst_output()
661 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
683 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
|
| /linux-6.3-rc2/drivers/gpu/drm/mediatek/ |
| A D | mtk_dp.c | 73 int lane_count; member
1143 u32 link_rate, int lane_count) in mtk_dp_phy_configure() argument
1150 .lanes = lane_count, in mtk_dp_phy_configure()
1311 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init()
1344 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init_in_hblank()
1370 mtk_dp->train_info.lane_count / in mtk_dp_setup_tu()
1680 lane_count = lane_count / 2; in mtk_dp_training()
1682 if (lane_count == 0) in mtk_dp_training()
1705 if (lane_count == 0) in mtk_dp_training()
1707 lane_count /= 2; in mtk_dp_training()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_link_encoder.c | 63 if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO) in dcn201_link_encoder_get_max_link_cap()
64 link_settings->lane_count = LANE_COUNT_TWO; in dcn201_link_encoder_get_max_link_cap()
|
| /linux-6.3-rc2/include/drm/display/ |
| A D | drm_dp_helper.h | 37 int lane_count);
39 int lane_count);
62 int lane_count);
64 int lane_count);
|