| /linux-6.3-rc2/tools/testing/selftests/drivers/net/mlxsw/ |
| A D | ethtool_lanes.sh | 55 local max_lanes=$1; shift
59 local unsupported_lanes=$((max_lanes *= 2))
73 local max_lanes
110 local max_lanes
115 max_lanes=${max_values[1]}
117 lanes=$max_lanes
134 check_unsupported_lanes $swp1 $max_speed $max_lanes 1
147 local max_lanes
152 max_lanes=${max_values[1]}
154 lanes=$max_lanes
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| /linux-6.3-rc2/tools/testing/selftests/net/ |
| A D | devlink_port_split.py | 156 max_lanes = get_max_lanes(port)
160 if max_lanes != lanes:
162 % (port, lanes, max_lanes))
259 max_lanes = get_max_lanes(port.name)
262 if max_lanes == 0:
266 elif max_lanes == 1:
269 split_unsplittable_port(port, max_lanes)
273 lane = max_lanes
277 split_splittable_port(port, lane, max_lanes, dev)
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| /linux-6.3-rc2/drivers/media/platform/cadence/ |
| A D | cdns-csi2rx.c | 75 u8 max_lanes; member
129 for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) { in csi2rx_start()
131 csi2rx->max_lanes); in csi2rx_start()
326 csi2rx->max_lanes = dev_cfg & 7; in csi2rx_get_resources()
327 if (csi2rx->max_lanes > CSI2RX_LANES_MAX) { in csi2rx_get_resources()
329 csi2rx->max_lanes); in csi2rx_get_resources()
395 if (csi2rx->num_lanes > csi2rx->max_lanes) { in csi2rx_parse_dt()
464 csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, in csi2rx_probe()
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| A D | cdns-csi2tx.c | 117 unsigned int max_lanes; member
466 csi2tx->max_lanes = dev_cfg & CSI2TX_DEVICE_CONFIG_LANES_MASK; in csi2tx_get_resources()
467 if (csi2tx->max_lanes > CSI2TX_LANES_MAX) { in csi2tx_get_resources()
469 csi2tx->max_lanes); in csi2tx_get_resources()
521 if (csi2tx->num_lanes > csi2tx->max_lanes) { in csi2tx_check_lanes()
628 csi2tx->num_lanes, csi2tx->max_lanes, csi2tx->max_streams, in csi2tx_probe()
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| /linux-6.3-rc2/drivers/gpu/drm/rockchip/ |
| A D | cdn-dp-reg.c | 539 dp->max_lanes = status[1]; in cdn_dp_get_training_status()
564 dp->max_lanes); in cdn_dp_train_link()
662 do_div(symbol, dp->max_lanes * link_rate * 8); in cdn_dp_config_video()
668 mode->clock, dp->max_lanes, link_rate); in cdn_dp_config_video()
682 val /= (dp->max_lanes * link_rate); in cdn_dp_config_video()
835 if (dp->max_lanes == 1) in cdn_dp_audio_config_i2s()
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| A D | cdn-dp-core.h | 98 u8 max_lanes; member
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| A D | cdn-dp-core.c | 490 dp->max_lanes = 0; in cdn_dp_disable()
583 if (!port || !dp->max_rate || !dp->max_lanes) in cdn_dp_check_link_status()
989 unsigned int lanes = dp->max_lanes; in cdn_dp_pd_event_work()
1002 (rate != dp->max_rate || lanes != dp->max_lanes)) { in cdn_dp_pd_event_work()
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| /linux-6.3-rc2/drivers/gpu/drm/tegra/ |
| A D | dp.c | 43 link->max_lanes = 0; in drm_dp_link_reset()
184 link->max_lanes = drm_dp_max_lane_count(dpcd); in drm_dp_link_probe()
233 link->lanes = link->max_lanes; in drm_dp_link_probe()
402 for (i = 0; i < ARRAY_SIZE(lanes) && lanes[i] <= link->max_lanes; i++) { in drm_dp_link_choose()
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| A D | dp.h | 125 unsigned int max_lanes; member
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| /linux-6.3-rc2/drivers/gpu/drm/i915/display/ |
| A D | intel_tc.c | 465 int max_lanes; in icl_tc_phy_connect() local
485 max_lanes = intel_tc_port_fia_max_lane_count(dig_port); in icl_tc_phy_connect()
487 drm_WARN_ON(&i915->drm, max_lanes != 4); in icl_tc_phy_connect()
503 if (max_lanes < required_lanes) { in icl_tc_phy_connect()
507 max_lanes, required_lanes); in icl_tc_phy_connect()
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| A D | intel_dp.c | 292 int max_lanes = dig_port->max_lanes; in intel_dp_max_source_lane_count() local
295 max_lanes = min(max_lanes, vbt_max_lanes); in intel_dp_max_source_lane_count()
297 return max_lanes; in intel_dp_max_source_lane_count()
384 return max_link_rate * max_lanes; in intel_dp_max_data_rate()
988 int max_rate, mode_rate, max_lanes, max_link_clock; in intel_dp_mode_valid() local
1018 max_lanes = intel_dp_max_lane_count(intel_dp); in intel_dp_mode_valid()
1049 max_lanes, in intel_dp_mode_valid()
2463 int max_lanes, rate_per_lane; in intel_dp_hdmi_sink_max_frl() local
2466 max_lanes = connector->display_info.hdmi.max_lanes; in intel_dp_hdmi_sink_max_frl()
2468 max_frl_rate = max_lanes * rate_per_lane; in intel_dp_hdmi_sink_max_frl()
[all …]
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| A D | intel_dp.h | 87 int intel_dp_max_data_rate(int max_link_rate, int max_lanes);
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| A D | intel_dp_mst.c | 858 int max_rate, mode_rate, max_lanes, max_link_clock; in intel_dp_mst_mode_valid_ctx() local
876 max_lanes = intel_dp_max_lane_count(intel_dp); in intel_dp_mst_mode_valid_ctx()
878 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); in intel_dp_mst_mode_valid_ctx()
918 max_lanes, in intel_dp_mst_mode_valid_ctx()
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| A D | intel_ddi.c | 1035 if (encoder->port == PORT_A && dig_port->max_lanes == 4) in skl_ddi_set_iboost()
4134 int max_lanes = 4; in intel_ddi_max_lanes() local
4137 return max_lanes; in intel_ddi_max_lanes()
4141 max_lanes = port == PORT_A ? 4 : 0; in intel_ddi_max_lanes()
4144 max_lanes = 2; in intel_ddi_max_lanes()
4156 max_lanes = 4; in intel_ddi_max_lanes()
4159 return max_lanes; in intel_ddi_max_lanes()
4507 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); in intel_ddi_init()
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| A D | g4x_hdmi.c | 628 dig_port->max_lanes = 4; in g4x_hdmi_init()
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| A D | intel_display_types.h | 1776 u8 max_lanes; member
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| A D | g4x_dp.c | 1361 dig_port->max_lanes = 4; in g4x_dp_init()
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| A D | intel_hdmi.c | 2950 if (drm_WARN(dev, dig_port->max_lanes < 4, in intel_hdmi_init_connector()
2952 dig_port->max_lanes, intel_encoder->base.base.id, in intel_hdmi_init_connector()
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| /linux-6.3-rc2/drivers/gpu/drm/xlnx/ |
| A D | zynqmp_dp.c | 247 u8 max_lanes; member
558 u8 max_lanes = dp->link_config.max_lanes; in zynqmp_dp_mode_configure() local
580 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) { in zynqmp_dp_mode_configure()
1382 dp->link_config.max_lanes, dp->config.bpp); in zynqmp_dp_bridge_mode_valid()
1428 dp->link_config.max_lanes, dp->config.bpp); in zynqmp_dp_bridge_atomic_enable()
1550 link_config->max_lanes = min_t(u8, in zynqmp_dp_bridge_detect()
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| /linux-6.3-rc2/include/drm/ |
| A D | drm_connector.h | 272 u8 max_lanes; member
314 u8 max_lanes; member
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| /linux-6.3-rc2/drivers/gpu/drm/gma500/ |
| A D | cdv_intel_dp.c | 371 cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes) in cdv_intel_dp_max_data_rate() argument
373 return (max_link_clock * max_lanes * 19) / 20; in cdv_intel_dp_max_data_rate()
513 int max_lanes = cdv_intel_dp_max_lane_count(encoder); in cdv_intel_dp_mode_valid() local
527 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes))) in cdv_intel_dp_mode_valid()
532 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)) in cdv_intel_dp_mode_valid()
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| /linux-6.3-rc2/drivers/gpu/drm/mediatek/ |
| A D | mtk_dp.c | 103 u8 max_lanes; member
1289 mtk_dp->train_info.lane_count = mtk_dp->max_lanes; in mtk_dp_initialize_priv_data()
1656 lane_count = min_t(u8, mtk_dp->max_lanes, in mtk_dp_training()
1906 mtk_dp->max_lanes = len; in mtk_dp_dt_parse()
2260 mtk_dp->max_lanes); in mtk_dp_bridge_mode_valid()
2306 mtk_dp->max_lanes); in mtk_dp_bridge_atomic_get_input_bus_fmts()
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| /linux-6.3-rc2/drivers/gpu/drm/ |
| A D | drm_edid.c | 5912 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) in drm_get_max_frl_rate() argument
5916 *max_lanes = 3; in drm_get_max_frl_rate()
5920 *max_lanes = 3; in drm_get_max_frl_rate()
5924 *max_lanes = 4; in drm_get_max_frl_rate()
5928 *max_lanes = 4; in drm_get_max_frl_rate()
5932 *max_lanes = 4; in drm_get_max_frl_rate()
5936 *max_lanes = 4; in drm_get_max_frl_rate()
5941 *max_lanes = 0; in drm_get_max_frl_rate()
5982 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, in drm_parse_dsc_info()
6076 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, in drm_parse_hdmi_forum_scds()
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| /linux-6.3-rc2/drivers/gpu/drm/bridge/analogix/ |
| A D | analogix_dp_core.c | 642 u32 max_lanes, u32 max_rate) in analogix_dp_full_link_train() argument
672 if (dp->link_train.lane_count > max_lanes) in analogix_dp_full_link_train()
673 dp->link_train.lane_count = max_lanes; in analogix_dp_full_link_train()
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| /linux-6.3-rc2/drivers/gpu/drm/display/ |
| A D | drm_dp_helper.c | 2586 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER); in drm_dp_lttpr_max_lane_count() local
2588 return max_lanes & DP_MAX_LANE_COUNT_MASK; in drm_dp_lttpr_max_lane_count()
3168 for (i = 0; i < hdmi->max_lanes; i++) { in drm_dp_pcon_hdmi_frl_link_error_count()
|