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Searched refs:pp_smu (Results 1 – 25 of 36) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/
A Ddm_pp_smu.h48 struct pp_smu { struct
97 struct pp_smu pp_smu; member
103 void (*set_display_count)(struct pp_smu *pp, int count);
112 void (*set_wm_ranges)(struct pp_smu *pp,
137 void (*set_pme_wa_enable)(struct pp_smu *pp);
168 struct pp_smu pp_smu; member
217 enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
269 struct pp_smu pp_smu; member
279 enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
287 struct pp_smu pp_smu; member
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
A Drv1_clk_mgr.c210 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_update_clocks()
224 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in rv1_update_clocks()
267 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
268 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
269 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_k… in rv1_update_clocks()
287 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
288 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
289 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_k… in rv1_update_clocks()
300 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_enable_pme_wa()
303 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); in rv1_enable_pme_wa()
[all …]
A Drv2_clk_mgr.c37 …gr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) in rv2_clk_mgr_construct() argument
40 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in rv2_clk_mgr_construct()
A Drv1_clk_mgr.h29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
A Drv2_clk_mgr.h29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
254 if (pp_smu && pp_smu->set_display_count) in dcn2_update_clocks()
255 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in dcn2_update_clocks()
264 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) in dcn2_update_clocks()
271 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) in dcn2_update_clocks()
292 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq) in dcn2_update_clocks()
317 if (pp_smu && pp_smu->set_voltage_by_freq) in dcn2_update_clocks()
417 pp_smu = &clk_mgr->pp_smu->nv_funcs; in dcn2_enable_pme_wa()
420 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); in dcn2_enable_pme_wa()
502 pp_smu = &clk_mgr->pp_smu->nv_funcs; in dcn2_notify_link_rate_change()
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A Ddcn20_clk_mgr.h43 struct pp_smu_funcs *pp_smu,
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/
A Dclk_mgr.c234 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
239 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
243 rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
248 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
261 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
265 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
269 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
276 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
287 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
300 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_pp_smu.c463 static void pp_rv_set_wm_ranges(struct pp_smu *pp, in pp_rv_set_wm_ranges()
512 static void pp_rv_set_pme_wa_enable(struct pp_smu *pp) in pp_rv_set_pme_wa_enable()
580 pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz) in pp_nv_set_min_deep_sleep_dcfclk()
597 struct pp_smu *pp, int mhz) in pp_nv_set_hard_min_dcefclk_by_freq()
620 pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz) in pp_nv_set_hard_min_uclk_by_freq()
643 struct pp_smu *pp, bool pstate_handshake_supported) in pp_nv_set_pstate_handshake_support()
691 struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks) in pp_nv_get_maximum_sustainable_clocks()
726 struct pp_smu *pp, struct dpm_clocks *clock_table) in pp_rn_get_dpm_clock_table()
760 funcs->rv_funcs.pp_smu.dm = ctx; in dm_pp_get_funcs()
774 funcs->nv_funcs.pp_smu.dm = ctx; in dm_pp_get_funcs()
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c515 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; in rn_notify_wm_ranges() local
521 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) in rn_notify_wm_ranges()
522 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
701 struct pp_smu_funcs *pp_smu, in rn_clk_mgr_construct() argument
716 clk_mgr->pp_smu = pp_smu; in rn_clk_mgr_construct()
777 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { in rn_clk_mgr_construct()
778 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); in rn_clk_mgr_construct()
A Drn_clk_mgr.h46 struct pp_smu_funcs *pp_smu,
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c805 if (pool->base.pp_smu != NULL) in dcn21_resource_destruct()
1140 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn21_pp_smu_create() local
1142 if (!pp_smu) in dcn21_pp_smu_create()
1143 return pp_smu; in dcn21_pp_smu_create()
1145 dm_pp_get_funcs(ctx, pp_smu); in dcn21_pp_smu_create()
1147 if (pp_smu->ctx.ver != PP_SMU_VER_RN) in dcn21_pp_smu_create()
1148 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn21_pp_smu_create()
1151 return pp_smu; in dcn21_pp_smu_create()
1156 if (pp_smu && *pp_smu) { in dcn21_pp_smu_destroy()
1157 kfree(*pp_smu); in dcn21_pp_smu_destroy()
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/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c2303 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC); in dcn20_pp_smu_create() local
2305 if (!pp_smu) in dcn20_pp_smu_create()
2306 return pp_smu; in dcn20_pp_smu_create()
2311 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn20_pp_smu_create()
2313 return pp_smu; in dcn20_pp_smu_create()
2318 if (pp_smu && *pp_smu) { in dcn20_pp_smu_destroy()
2319 kfree(*pp_smu); in dcn20_pp_smu_destroy()
2320 *pp_smu = NULL; in dcn20_pp_smu_destroy()
2372 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()
2379 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); in init_soc_bounding_box()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
A Ddcn201_clk_mgr.h31 struct pp_smu_funcs *pp_smu,
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.h32 struct pp_smu_funcs *pp_smu,
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
A Ddcn315_clk_mgr.h44 struct pp_smu_funcs *pp_smu,
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
A Ddcn316_clk_mgr.h44 struct pp_smu_funcs *pp_smu,
A Ddcn316_clk_mgr.c617 struct pp_smu_funcs *pp_smu, in dcn316_clk_mgr_construct() argument
625 clk_mgr->base.pp_smu = pp_smu; in dcn316_clk_mgr_construct()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.h47 struct pp_smu_funcs *pp_smu,
A Dvg_clk_mgr.c663 struct pp_smu_funcs *pp_smu, in vg_clk_mgr_construct() argument
671 clk_mgr->base.pp_smu = pp_smu; in vg_clk_mgr_construct()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_resource.c906 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn10_pp_smu_create() local
908 if (!pp_smu) in dcn10_pp_smu_create()
909 return pp_smu; in dcn10_pp_smu_create()
911 dm_pp_get_funcs(ctx, pp_smu); in dcn10_pp_smu_create()
912 return pp_smu; in dcn10_pp_smu_create()
991 kfree(pool->base.pp_smu); in dcn10_resource_destruct()
1494 pool->base.pp_smu = dcn10_pp_smu_create(ctx); in dcn10_resource_construct()
1500 if (pool->base.pp_smu != NULL in dcn10_resource_construct()
1501 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) in dcn10_resource_construct()
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A Ddcn314_clk_mgr.h52 struct pp_smu_funcs *pp_smu,
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.h51 struct pp_smu_funcs *pp_smu,
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.h93 struct pp_smu_funcs *pp_smu,
/linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_resource.c1346 struct pp_smu_funcs *pp_smu, in set_wm_ranges() argument
1386 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); in set_wm_ranges()
1574 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) in dcn301_resource_construct()
1575 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); in dcn301_resource_construct()

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