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Searched refs:rb_bufsz (Results 1 – 25 of 42) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Duvd_v1_0.c266 uint32_t rb_bufsz; in uvd_v1_0_start() local
377 rb_bufsz = order_base_2(ring->ring_size); in uvd_v1_0_start()
378 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v1_0_start()
379 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
A Dni_dma.c190 u32 rb_bufsz; in cayman_dma_resume() local
209 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
210 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
A Dr600_dma.c123 u32 rb_bufsz; in r600_dma_resume() local
130 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
131 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
A Dcik_sdma.c368 u32 rb_bufsz; in cik_sdma_gfx_resume() local
387 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
388 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
A Dr600.c2720 u32 rb_bufsz; in r600_cp_resume() local
2730 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2782 u32 rb_bufsz; in r600_ring_init() local
2786 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()
2787 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()
3468 u32 rb_bufsz; in r600_ih_ring_init() local
3471 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()
3472 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()
3674 int rb_bufsz; in r600_irq_init() local
3708 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in r600_irq_init()
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/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_ih.c44 u32 rb_bufsz; in amdgpu_ih_ring_init() local
48 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
49 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
A Dsi_ih.c65 int rb_bufsz; in si_ih_irq_init() local
77 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
81 (rb_bufsz << 1) | in si_ih_irq_init()
A Dcik_ih.c109 int rb_bufsz; in cik_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
131 (rb_bufsz << 1)); in cik_ih_irq_init()
A Duvd_v3_1.c323 uint32_t rb_bufsz; in uvd_v3_1_start() local
433 rb_bufsz = order_base_2(ring->ring_size); in uvd_v3_1_start()
434 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v3_1_start()
435 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v3_1_start()
A Duvd_v4_2.c281 uint32_t rb_bufsz; in uvd_v4_2_start() local
391 rb_bufsz = order_base_2(ring->ring_size); in uvd_v4_2_start()
392 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v4_2_start()
393 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
A Dcz_ih.c110 int rb_bufsz; in cz_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
A Diceland_ih.c109 int rb_bufsz; in iceland_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
A Dtonga_ih.c106 int rb_bufsz; in tonga_ih_irq_init() local
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
A Duvd_v5_0.c318 uint32_t rb_bufsz, tmp; in uvd_v5_0_start() local
415 rb_bufsz = order_base_2(ring->ring_size); in uvd_v5_0_start()
417 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
A Dvcn_v2_5.c805 uint32_t rb_bufsz, tmp; in vcn_v2_5_start_dpg_mode() local
903 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start_dpg_mode()
904 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start_dpg_mode()
950 uint32_t rb_bufsz, tmp; in vcn_v2_5_start() local
1095 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start()
1096 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
1199 uint32_t offset, size, tmp, i, rb_bufsz; in vcn_v2_5_sriov_start() local
1314 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_sriov_start()
1315 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_sriov_start()
A Dsi_dma.c131 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local
142 rb_bufsz = order_base_2(ring->ring_size / 4); in si_dma_start()
143 rb_cntl = rb_bufsz << 1; in si_dma_start()
A Dvega10_ih.c160 int rb_bufsz = order_base_2(ih->ring_size / 4); in vega10_ih_rb_cntl() local
168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega10_ih_rb_cntl()
A Dvcn_v1_0.c790 uint32_t rb_bufsz, tmp; in vcn_v1_0_start_spg_mode() local
909 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_spg_mode()
910 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_spg_mode()
964 uint32_t rb_bufsz, tmp; in vcn_v1_0_start_dpg_mode() local
1067 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_dpg_mode()
1068 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_dpg_mode()
A Dvcn_v2_0.c797 uint32_t rb_bufsz, tmp; in vcn_v2_0_start_dpg_mode() local
887 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start_dpg_mode()
888 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start_dpg_mode()
934 uint32_t rb_bufsz, tmp; in vcn_v2_0_start() local
1059 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start()
1060 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start()
A Dih_v6_0.c189 int rb_bufsz = order_base_2(ih->ring_size / 4); in ih_v6_0_rb_cntl() local
197 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in ih_v6_0_rb_cntl()
A Dnavi10_ih.c215 int rb_bufsz = order_base_2(ih->ring_size / 4); in navi10_ih_rb_cntl() local
223 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in navi10_ih_rb_cntl()
A Dvega20_ih.c164 int rb_bufsz = order_base_2(ih->ring_size / 4); in vega20_ih_rb_cntl() local
172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega20_ih_rb_cntl()
A Dsdma_v2_4.c406 u32 rb_bufsz; in sdma_v2_4_gfx_resume() local
428 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v2_4_gfx_resume()
430 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
A Dcik_sdma.c430 u32 rb_bufsz; in cik_sdma_gfx_resume() local
454 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
455 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
A Dvcn_v3_0.c944 uint32_t rb_bufsz, tmp; in vcn_v3_0_start_dpg_mode() local
1044 rb_bufsz = order_base_2(ring->ring_size); in vcn_v3_0_start_dpg_mode()
1045 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start_dpg_mode()
1098 uint32_t rb_bufsz, tmp; in vcn_v3_0_start() local
1231 rb_bufsz = order_base_2(ring->ring_size); in vcn_v3_0_start()
1232 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start()

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