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Searched refs:reg_access_ctrl (Results 1 – 5 of 5) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_virt.c959 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in amdgpu_virt_rlcg_reg_rw() local
975 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; in amdgpu_virt_rlcg_reg_rw()
976 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; in amdgpu_virt_rlcg_reg_rw()
977 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; in amdgpu_virt_rlcg_reg_rw()
978 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; in amdgpu_virt_rlcg_reg_rw()
979 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; in amdgpu_virt_rlcg_reg_rw()
980 if (reg_access_ctrl->spare_int) in amdgpu_virt_rlcg_reg_rw()
981 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; in amdgpu_virt_rlcg_reg_rw()
983 if (offset == reg_access_ctrl->grbm_cntl) { in amdgpu_virt_rlcg_reg_rw()
988 } else if (offset == reg_access_ctrl->grbm_idx) { in amdgpu_virt_rlcg_reg_rw()
[all …]
A Damdgpu_rlc.h260 struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl; member
A Dgfx_v9_0.c1633 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v9_0_init_rlcg_reg_access_ctrl() local
1635 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1636 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1637 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1638 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1639 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1640 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1641 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1642 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); in gfx_v9_0_init_rlcg_reg_access_ctrl()
A Dgfx_v11_0.c646 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v11_0_init_rlcg_reg_access_ctrl() local
648 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; in gfx_v11_0_init_rlcg_reg_access_ctrl()
649 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
650 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v11_0_init_rlcg_reg_access_ctrl()
651 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v11_0_init_rlcg_reg_access_ctrl()
652 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v11_0_init_rlcg_reg_access_ctrl()
653 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_init_rlcg_reg_access_ctrl()
654 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
655 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
A Dgfx_v10_0.c4152 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v10_0_init_rlcg_reg_access_ctrl() local
4154 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; in gfx_v10_0_init_rlcg_reg_access_ctrl()
4155 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4156 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4157 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4158 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4159 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4160 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4163 reg_access_ctrl->spare_int = in gfx_v10_0_init_rlcg_reg_access_ctrl()
4167 reg_access_ctrl->spare_int = in gfx_v10_0_init_rlcg_reg_access_ctrl()

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