| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn303/ |
| A D | dcn303_resource.c | 669 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
704 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
955 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
985 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
998 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
1010 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
1034 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1150 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct()
1318 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_construct()
1363 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_construct()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn302/ |
| A D | dcn302_resource.c | 726 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
761 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1029 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1059 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1072 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1084 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
1108 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1227 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct()
1405 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_construct()
1450 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_construct()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn316/ |
| A D | dcn316_resource.c | 1414 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct()
1444 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn316_resource_destruct()
1457 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_destruct()
1469 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1492 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn316_resource_destruct()
1542 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1567 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
1767 pool->base.res_cap = &res_cap_dcn31; in dcn316_resource_construct()
1940 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_construct()
1990 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_construct()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 1078 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1108 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct()
1121 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct()
1126 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1133 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1156 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct()
1201 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1226 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
1438 pool->base.res_cap = &res_cap_dcn301; in dcn301_resource_construct()
1672 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_resource_construct()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn314/ |
| A D | dcn314_resource.c | 1448 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct()
1477 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn314_resource_destruct()
1490 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_destruct()
1502 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1525 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn314_resource_destruct()
1575 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1600 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
1815 pool->base.res_cap = &res_cap_dcn314; in dcn314_resource_construct()
1989 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_construct()
2039 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_construct()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn315/ |
| A D | dcn315_resource.c | 1413 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_destruct()
1443 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn315_resource_destruct()
1456 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_destruct()
1468 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1491 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn315_resource_destruct()
1541 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1566 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
1768 pool->base.res_cap = &res_cap_dcn31; in dcn315_resource_construct()
1941 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_construct()
1991 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_construct()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.c | 1415 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
1445 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
1458 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
1470 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1493 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1543 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1568 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
1904 pool->base.res_cap = &res_cap_dcn31; in dcn31_resource_construct()
2095 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_construct()
2145 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_construct()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn321/ |
| A D | dcn321_resource.c | 1390 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_destruct()
1419 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn321_resource_destruct()
1432 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn321_resource_destruct()
1444 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1502 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1531 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
1668 pool->base.res_cap = &res_cap_dcn321; in dcn321_resource_construct()
1670 num_pipes = pool->base.res_cap->num_timing_generator; in dcn321_resource_construct()
1927 …pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_… in dcn321_resource_construct()
1935 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_construct()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_resource.c | 1105 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1135 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1148 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1160 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1236 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1261 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1464 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
2287 pool->base.res_cap = &res_cap_dcn3; in dcn30_resource_construct()
2483 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_construct()
2532 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_construct()
[all …]
|
| A D | dcn30_hwseq.c | 390 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
420 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
538 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn30_init_hw()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce60/ |
| A D | dce60_resource.c | 372 static const struct resource_caps res_cap = { variable
822 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
952 pool->base.res_cap = &res_cap; in dce60_construct()
960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
961 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1073 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1147 pool->base.res_cap = &res_cap_61; in dce61_construct()
1271 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1345 pool->base.res_cap = &res_cap_64; in dce64_construct()
1465 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce80/ |
| A D | dce80_resource.c | 375 static const struct resource_caps res_cap = { variable
825 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
955 pool->base.res_cap = &res_cap; in dce80_construct()
963 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
964 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1082 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1156 pool->base.res_cap = &res_cap_81; in dce81_construct()
1282 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1356 pool->base.res_cap = &res_cap_83; in dce83_construct()
1478 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn32/ |
| A D | dcn32_resource.c | 1404 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_destruct()
1434 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn32_resource_destruct()
1447 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn32_resource_destruct()
1459 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1517 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1546 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
1639 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn32_release_post_bldn_3dlut()
2115 pool->base.res_cap = &res_cap_dcn32; in dcn32_resource_construct()
2386 …pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_ca… in dcn32_resource_construct()
2394 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_construct()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce100/ |
| A D | dce100_resource.c | 374 static const struct resource_caps res_cap = { variable
777 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
989 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1064 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1065 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1120 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.c | 1120 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1150 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
1163 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1175 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
1343 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1357 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1371 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
2254 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
2277 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
2426 pool->base.res_cap = &res_cap_nv14; in dcn20_resource_construct()
[all …]
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_link_enc_cfg.c | 40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
177 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
260 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
526 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc()
693 for (j = 0; j < dc->res_pool->res_cap->num_dig_link_enc; j++) { in link_enc_cfg_validate()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 706 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
736 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
749 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
754 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
761 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
1436 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct()
1440 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; in dcn21_resource_construct()
1451 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1669 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
1705 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_construct()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce120/ |
| A D | dce120_resource.c | 497 static const struct resource_caps res_cap = { variable
624 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1066 pool->base.res_cap = &res_cap; in dce120_resource_construct()
1070 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1071 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1216 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_resource.c | 953 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct()
958 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1095 pool->base.res_cap = &res_cap_dnc201; in dcn201_resource_construct()
1193 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1228 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct()
1237 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct()
1253 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
|
| A D | dcn201_hwseq.c | 183 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
307 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw()
340 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_resource.c | 485 static const struct resource_caps res_cap = { variable
959 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1329 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct()
1331 pool->base.res_cap = &res_cap; in dcn10_resource_construct()
1345 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1613 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce112/ |
| A D | dce112_resource.c | 798 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1226 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct()
1233 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1234 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1367 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_resource.c | 836 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_destruct()
1357 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in dce110_resource_construct()
1364 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1366 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1481 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_construct()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | dcn31_fpu.c | 583 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box()
659 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box()
731 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box()
|
| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 311 const struct resource_caps *res_cap; member
|