/linux-6.3-rc2/drivers/mmc/host/ |
A D | sdhci-xenon-phy.c | 235 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init() 265 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init() 331 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll() 336 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll() 420 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_disable_strobe() 454 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_strobe_delay_adj() 556 reg = sdhci_readl(host, phy_regs->pad_ctrl); in xenon_emmc_phy_set() 600 reg = sdhci_readl(host, phy_regs->pad_ctrl2); in xenon_emmc_phy_set() 609 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_emmc_phy_set() 613 reg = sdhci_readl(host, phy_regs->func_ctrl); in xenon_emmc_phy_set() [all …]
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A D | sdhci-of-esdhc.c | 853 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_reset() 903 val = sdhci_readl(host, ESDHC_PROCTL); in esdhc_signal_voltage_switch() 965 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_tuning_block_enable() 981 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_tuning_window_ptr() 989 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_tuning_window_ptr() 995 val = sdhci_readl(host, ESDHC_TBSTAT); in esdhc_tuning_window_ptr() 996 val = sdhci_readl(host, ESDHC_TBSTAT); in esdhc_tuning_window_ptr() 1053 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_execute_sw_tuning() 1103 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_execute_tuning() 1186 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_set_uhs_signaling() [all …]
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A D | sdhci_f_sdh30.c | 38 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch() 50 ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_soft_voltage_switch() 55 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_f_sdh30_soft_voltage_switch() 76 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_reset() 82 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { in sdhci_f_sdh30_reset() 83 ctl = sdhci_readl(host, F_SDH30_TEST); in sdhci_f_sdh30_reset() 182 reg = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe() 187 reg = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_f_sdh30_probe()
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A D | sdhci-xenon.c | 30 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk() 58 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_sdclk_off_idle() 74 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_acg() 88 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_enable_sdhc() 106 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_disable_sdhc() 117 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_enable_sdhc_parallel_tran() 127 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err() 144 reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); in xenon_retune_setup() 147 reg = sdhci_readl(host, SDHCI_INT_ENABLE); in xenon_retune_setup() 389 reg = sdhci_readl(host, XENON_SYS_CFG_INFO); in xenon_enable_sdio_irq() [all …]
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A D | sdhci-bcm-kona.c | 57 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset() 61 while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) { in sdhci_bcm_kona_sd_reset() 69 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset() 89 val = sdhci_readl(host, KONA_SDHOST_COREIMR); in sdhci_bcm_kona_sd_init() 94 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_init() 128 val = sdhci_readl(host, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
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A D | sdhci-pci-dwc-mshc.c | 39 reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr)); in sdhci_snps_set_clock() 47 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock() 63 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
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A D | sdhci-milbeaut.c | 65 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch() 75 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_milbeaut_soft_voltage_switch() 118 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_reset() 149 val = sdhci_readl(host, MLB_CR_SET); in sdhci_milbeaut_bridge_init() 181 ctl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init() 196 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_vendor_init()
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A D | sdhci-pci-gli.c | 160 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_on() 177 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_off() 202 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750() 204 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750() 289 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750_rx_inv() 361 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_disable_ssc_pll() 372 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_set_pll() 392 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gl9750_ssc_enable() 405 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_set_ssc() 406 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc() [all …]
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A D | sdhci-sprd.c | 113 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); in sdhci_sprd_init_config() 187 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); in sdhci_sprd_set_dll_invert() 233 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock() 247 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll() 253 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll() 260 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll() 266 if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED), in sdhci_sprd_enable_phy_dll() 271 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0), in sdhci_sprd_enable_phy_dll() 272 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG)); in sdhci_sprd_enable_phy_dll()
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A D | sdhci-pci-o2micro.c | 89 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_o2_wait_card_detect_stable() 111 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock() 145 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock() 159 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in sdhci_o2_get_cd() 178 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_pll_dll_wdt_control() 258 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery() 616 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_pci_o2_probe_slot() 631 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); in sdhci_pci_o2_probe_slot() 669 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
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A D | sdhci-tegra.c | 353 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_set_tap() 431 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_configure_cal_pad() 449 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_set_pad_autocal_offset() 494 reg = sdhci_readl(host, in tegra_sdhci_set_padctrl() 558 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib() 576 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib() 841 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); in tegra_sdhci_hs400_dll_cal() 878 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); in tegra_sdhci_tap_correction() 949 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_post_tuning() 1042 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); in tegra_sdhci_set_uhs_signaling() [all …]
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A D | sdhci.c | 59 sdhci_readl(host, SDHCI_DMA_ADDRESS), in sdhci_dumpregs() 65 sdhci_readl(host, SDHCI_ARGUMENT), in sdhci_dumpregs() 68 sdhci_readl(host, SDHCI_PRESENT_STATE), in sdhci_dumpregs() 78 sdhci_readl(host, SDHCI_INT_STATUS)); in sdhci_dumpregs() 80 sdhci_readl(host, SDHCI_INT_ENABLE), in sdhci_dumpregs() 86 sdhci_readl(host, SDHCI_CAPABILITIES), in sdhci_dumpregs() 90 sdhci_readl(host, SDHCI_MAX_CURRENT)); in sdhci_dumpregs() 92 sdhci_readl(host, SDHCI_RESPONSE), in sdhci_dumpregs() 95 sdhci_readl(host, SDHCI_RESPONSE + 8), in sdhci_dumpregs() 103 sdhci_readl(host, SDHCI_ADMA_ERROR), in sdhci_dumpregs() [all …]
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A D | sdhci-brcmstb.c | 49 reg = sdhci_readl(host, SDHCI_VENDOR); in enable_clock_gating() 136 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable() 138 sdhci_readl(host, SDHCI_BUFFER); in sdhci_brcmstb_cqe_enable() 139 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable()
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A D | sdhci-of-sparx5.c | 236 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION)); in sdhci_sparx5_probe() 238 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE)); in sdhci_sparx5_probe()
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A D | sdhci-of-arasan.c | 356 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); in sdhci_arasan_hs400_enhanced_strobe() 435 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable() 437 sdhci_readl(host, SDHCI_BUFFER); in sdhci_arasan_cqe_enable() 438 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable() 813 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase() 880 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
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A D | sdhci-of-dwcmshc.c | 196 vendor = sdhci_readl(host, reg); in dwcmshc_hs400_enhanced_strobe() 234 extra = sdhci_readl(host, reg); in dwcmshc_rk3568_set_clock() 513 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; in dwcmshc_probe()
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A D | sdhci-of-at91.c | 126 u32 calcr = sdhci_readl(host, SDMMC_CALCR); in sdhci_at91_reset() 131 if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN), in sdhci_at91_reset()
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A D | sdhci-acpi.c | 315 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 && in intel_probe_slot() 316 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807) in intel_probe_slot() 935 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0); in sdhci_acpi_remove()
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A D | sdhci.h | 692 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function 733 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
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A D | sdhci-esdhc-imx.c | 959 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock() 986 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock() 1541 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in esdhc_cqe_enable() 1543 sdhci_readl(host, SDHCI_BUFFER); in esdhc_cqe_enable() 1544 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in esdhc_cqe_enable()
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A D | sdhci-pci-core.c | 645 val = sdhci_readl(host, INTEL_HS400_ES_REG); in intel_hs400_enhanced_strobe() 1004 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); in glk_rpm_retune_wa() 1005 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); in glk_rpm_retune_wa() 1757 return sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_read_present_state()
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A D | sdhci-of-aspeed.c | 102 cap_val = sdhci_readl(host, 0x40 + (cap_reg * 4)); in aspeed_sdc_set_slot_capability()
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A D | sdhci-msm.c | 2084 ctrl = sdhci_readl(host, SDHCI_INT_ENABLE); in sdhci_msm_cqe_disable()
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