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Searched refs:spx5_wr (Results 1 – 16 of 16) sorted by relevance

/linux-6.3-rc2/drivers/net/ethernet/microchip/sparx5/
A Dsparx5_vlan.c18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
19 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
143 spx5_wr(0, spx5, ANA_AC_PGID_CFG(pgid)); in sparx5_pgid_clear()
144 spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid)); in sparx5_pgid_clear()
145 spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid)); in sparx5_pgid_clear()
182 spx5_wr(0, sparx5, ANA_AC_SRC_CFG(port)); in sparx5_update_fwd()
183 spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port)); in sparx5_update_fwd()
184 spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port)); in sparx5_update_fwd()
194 spx5_wr(mask[0], sparx5, ANA_L2_AUTO_LRN_CFG); in sparx5_update_fwd()
195 spx5_wr(mask[1], sparx5, ANA_L2_AUTO_LRN_CFG1); in sparx5_update_fwd()
[all …]
A Dsparx5_vcap_impl.c937 spx5_wr(~mskstr[idx], sparx5, in sparx5_vcap_is0_cache_write()
943 spx5_wr(actstr[idx], sparx5, in sparx5_vcap_is0_cache_write()
978 spx5_wr(~mskstr[idx], sparx5, in sparx5_vcap_is2_cache_write()
984 spx5_wr(actstr[idx], sparx5, in sparx5_vcap_is2_cache_write()
1038 spx5_wr(~mskstr[idx], sparx5, in sparx5_vcap_es0_cache_write()
1044 spx5_wr(actstr[idx], sparx5, in sparx5_vcap_es0_cache_write()
1079 spx5_wr(~mskstr[idx], sparx5, in sparx5_vcap_es2_cache_write()
1085 spx5_wr(actstr[idx], sparx5, in sparx5_vcap_es2_cache_write()
1538 spx5_wr(keysel, sparx5, in sparx5_vcap_is0_port_key_selection()
1563 spx5_wr(keysel, sparx5, in sparx5_vcap_is2_port_key_selection()
[all …]
A Dsparx5_fdma.c116 spx5_wr(((u64)rx->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_rx_activate()
162 spx5_wr(((u64)tx->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_tx_activate()
190 spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_RELOAD); in sparx5_fdma_rx_reload()
196 spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_RELOAD); in sparx5_fdma_tx_reload()
471 spx5_wr(0, sparx5, FDMA_INTR_DB_ENA); in sparx5_fdma_handler()
472 spx5_wr(db, sparx5, FDMA_INTR_DB); in sparx5_fdma_handler()
481 spx5_wr(err, sparx5, FDMA_INTR_ERR); in sparx5_fdma_handler()
482 spx5_wr(err_type, sparx5, FDMA_ERRORS); in sparx5_fdma_handler()
494 spx5_wr(QS_XTR_GRP_CFG_MODE_SET(2) | in sparx5_fdma_injection_mode()
498 spx5_wr(QS_INJ_GRP_CFG_MODE_SET(2) | in sparx5_fdma_injection_mode()
[all …]
A Dsparx5_psfp.c105 spx5_wr(ANA_AC_SG_ACCESS_CTRL_SGID_SET(id), sparx5, in sparx5_psfp_sg_config_change()
108 spx5_wr(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(1) | in sparx5_psfp_sg_config_change()
143 spx5_wr(ANA_AC_SG_ACCESS_CTRL_SGID_SET(id), sparx5, in sparx5_psfp_sg_set()
147 spx5_wr(sg->basetime.tv_nsec, sparx5, ANA_AC_SG_CONFIG_REG_1); in sparx5_psfp_sg_set()
148 spx5_wr(base_lsb, sparx5, ANA_AC_SG_CONFIG_REG_2); in sparx5_psfp_sg_set()
162 spx5_wr(sg->cycletime, sparx5, ANA_AC_SG_CONFIG_REG_4); in sparx5_psfp_sg_set()
163 spx5_wr(sg->cycletimeext, sparx5, ANA_AC_SG_CONFIG_REG_5); in sparx5_psfp_sg_set()
172 spx5_wr(ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(ips) | in sparx5_psfp_sg_set()
177 spx5_wr(accum_time_interval, sparx5, in sparx5_psfp_sg_set()
181 spx5_wr(gce->maxoctets, sparx5, ANA_AC_SG_GCL_OCT_CONFIG(i)); in sparx5_psfp_sg_set()
[all …]
A Dsparx5_packet.c26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
32 spx5_wr(0, sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
179 spx5_wr(QS_INJ_CTRL_SOF_SET(1) | in sparx5_inject()
185 spx5_wr(ifh[w], sparx5, QS_INJ_WR(grp)); in sparx5_inject()
192 spx5_wr(val, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
197 spx5_wr(0, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
202 spx5_wr(QS_INJ_CTRL_GAP_SIZE_SET(1) | in sparx5_inject()
208 spx5_wr(0, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
305 spx5_wr(QS_XTR_GRP_CFG_MODE_SET(1) | in sparx5_manual_injection_mode()
309 spx5_wr(QS_INJ_GRP_CFG_MODE_SET(1) | in sparx5_manual_injection_mode()
[all …]
A Dsparx5_mactable.c76 spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0); in sparx5_mact_select()
77 spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1); in sparx5_mact_select()
99 spx5_wr(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(addr) | in sparx5_mact_learn()
104 spx5_wr(0, sparx5, LRN_MAC_ACCESS_CFG_3); in sparx5_mact_learn()
107 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_LEARN) | in sparx5_mact_learn()
169 spx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(1) | in sparx5_mact_getnext()
172 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET in sparx5_mact_getnext()
200 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_LOOKUP) | in sparx5_mact_find()
228 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_UNLEARN) | in sparx5_mact_forget()
443 spx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(1), in sparx5_mact_pull_work()
[all …]
A Dsparx5_main.c552 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
556 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
561 spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); in sparx5_qlim_set()
562 spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); in sparx5_qlim_set()
589 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, in sparx5_board_init()
603 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); in sparx5_start()
604 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); in sparx5_start()
605 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); in sparx5_start()
606 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx)); in sparx5_start()
620 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), in sparx5_start()
[all …]
A Dsparx5_ptp.c426 spx5_wr((u32)tod_inc & 0xFFFFFFFF, sparx5, in sparx5_ptp_adjfine()
428 spx5_wr((u32)(tod_inc >> 32), sparx5, in sparx5_ptp_adjfine()
459 spx5_wr(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(upper_32_bits(ts->tv_sec)), in sparx5_ptp_settime64()
461 spx5_wr(lower_32_bits(ts->tv_sec), in sparx5_ptp_settime64()
463 spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); in sparx5_ptp_settime64()
535 spx5_wr(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(delta), in sparx5_ptp_adjtime()
614 spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0), sparx5, PTP_PTP_DOM_CFG); in sparx5_ptp_init()
622 spx5_wr((u32)tod_adj & 0xFFFFFFFF, sparx5, in sparx5_ptp_init()
624 spx5_wr((u32)(tod_adj >> 32), sparx5, in sparx5_ptp_init()
633 spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0x7), sparx5, PTP_PTP_DOM_CFG); in sparx5_ptp_init()
A Dsparx5_sdlb.c244 spx5_wr(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(next) | in sparx5_sdlb_group_link()
249 spx5_wr(ANA_AC_SDLB_XLB_START_LBSET_START_SET(first), sparx5, in sparx5_sdlb_group_link()
327 spx5_wr(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(group->pup_interval), in sparx5_sdlb_group_init()
330 spx5_wr(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(frame_size), in sparx5_sdlb_group_init()
333 spx5_wr(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(thres_shift), sparx5, in sparx5_sdlb_group_init()
A Dsparx5_port.c90 spx5_wr(value, sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
571 spx5_wr(DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(etype) | in sparx5_port_max_tags_set()
756 spx5_wr(DEV2G5_PCS1G_CFG_PCS_ENA_SET(1), in sparx5_port_pcs_low_set()
764 spx5_wr(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(abil) | in sparx5_port_pcs_low_set()
771 spx5_wr(0, sparx5, DEV2G5_PCS1G_ANEG_CFG(port->portno)); in sparx5_port_pcs_low_set()
890 spx5_wr(DEV2G5_MAC_IFG_CFG_TX_IFG_SET(tx_gap) | in sparx5_port_config_low_set()
903 spx5_wr(DEV2G5_MAC_ENA_CFG_RX_ENA | in sparx5_port_config_low_set()
1050 spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | in sparx5_port_init()
1067 spx5_wr(QSYS_ATOP_ATOP_SET(atop), in sparx5_port_init()
1102 spx5_wr(DEV2G5_MAC_IFG_CFG_TX_IFG_SET(6) | in sparx5_port_init()
[all …]
A Dsparx5_calendar.c217 spx5_wr(cal[idx], sparx5, QSYS_CAL_AUTO(idx)); in sparx5_config_auto_calendar()
229 spx5_wr(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(12), in sparx5_config_auto_calendar()
539 spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), in sparx5_dsm_calendar_update()
552 spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0), in sparx5_dsm_calendar_update()
A Dsparx5_police.c29 spx5_wr(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(pup_tokens), sparx5, in sparx5_policer_service_conf_set()
A Dsparx5_qos.c90 spx5_wr(HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(leak_time), sparx5, in sparx5_lg_set_leak_time()
252 spx5_wr(HSCH_SE_CONNECT_SE_LEAK_LINK_SET(idx_next), sparx5, in sparx5_lg_conf_set()
346 spx5_wr(HSCH_CIR_CFG_CIR_RATE_SET(sh->rate) | in sparx5_shaper_conf_set()
A Dsparx5_vcap_debugfs.c282 spx5_wr(value, sparx5, ANA_ACL_SEC_LOOKUP_STICKY(lookup)); in sparx5_vcap_is2_port_stickies()
433 spx5_wr(value, sparx5, EACL_SEC_LOOKUP_STICKY(lookup)); in sparx5_vcap_es2_port_stickies()
A Dsparx5_main.h627 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, in spx5_wr() function
A Dsparx5_ethtool.c210 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno), sparx5, XQS_STAT_CFG); in sparx5_get_queue_sys_stats()
1172 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno) | in sparx5_config_port_stats()

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