| /linux-6.3-rc2/drivers/gpu/drm/i915/display/ |
| A D | intel_dkl_phy_regs.h | 29 #define _DKL_REG_PHY_BASE(tc_port) _PORT(tc_port, \ argument
51 #define DKL_PCS_DW5(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ argument
57 #define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \ argument
76 #define DKL_PLL_DIV1(tc_port) _DKL_REG(tc_port, \ argument
84 #define DKL_PLL_SSC(tc_port) _DKL_REG(tc_port, \ argument
95 #define DKL_PLL_BIAS(tc_port) _DKL_REG(tc_port, \ argument
103 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _DKL_REG(tc_port, \ argument
111 #define DKL_REFCLKIN_CTL(tc_port) _DKL_REG(tc_port, \ argument
121 #define DKL_CLKTOP2_CORECLKCTL1(tc_port) _DKL_REG(tc_port, \ argument
187 #define DKL_CMN_UC_DW_27(tc_port) _DKL_REG(tc_port, \ argument
[all …]
|
| A D | intel_mg_phy_regs.h | 105 #define MG_CLKHUB(ln, tc_port) \ argument
161 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \ argument
171 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \ argument
189 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \ argument
201 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \ argument
214 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \ argument
225 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \ argument
236 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \ argument
248 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \ argument
266 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \ argument
[all …]
|
| A D | intel_dkl_phy.c | 17 enum tc_port tc_port = DKL_REG_TC_PORT(reg); in dkl_phy_set_hip_idx() local
19 drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); in dkl_phy_set_hip_idx()
22 HIP_INDEX_REG(tc_port), in dkl_phy_set_hip_idx()
23 HIP_INDEX_VAL(tc_port, reg.bank_idx)); in dkl_phy_set_hip_idx()
|
| A D | intel_tc.c | 274 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); in adl_tc_port_live_status_mask() local
283 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in adl_tc_port_live_status_mask()
343 enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port); in adl_tc_phy_status_complete() local
346 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in adl_tc_phy_status_complete()
904 enum tc_port tc_port = intel_port_to_tc(i915, port); in tc_port_load_fia_params() local
911 dig_port->tc_phy_fia = tc_port / 2; in tc_port_load_fia_params()
912 dig_port->tc_phy_fia_idx = tc_port % 2; in tc_port_load_fia_params()
915 dig_port->tc_phy_fia_idx = tc_port; in tc_port_load_fia_params()
923 enum tc_port tc_port = intel_port_to_tc(i915, port); in intel_tc_port_init() local
925 if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE)) in intel_tc_port_init()
[all …]
|
| A D | intel_dpll_mgr.c | 183 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) in icl_tc_port_to_pll_id() argument
205 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in intel_tc_pll_enable_reg() local
208 return ADLP_PORTTC_PLL_ENABLE(tc_port); in intel_tc_pll_enable_reg()
210 return MG_PLL_ENABLE(tc_port); in intel_tc_pll_enable_reg()
3401 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in mg_pll_get_hw_state() local
3418 MG_REFCLKIN_CTL(tc_port)); in mg_pll_get_hw_state()
3438 MG_PLL_FRAC_LOCK(tc_port)); in mg_pll_get_hw_state()
3467 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in dkl_pll_get_hw_state() local
3486 DKL_REFCLKIN_CTL(tc_port)); in dkl_pll_get_hw_state()
3653 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); in icl_mg_pll_write() local
[all …]
|
| A D | intel_ddi.c | 1199 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); in icl_mg_phy_set_signal_levels() local
1300 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); in tgl_dkl_phy_set_signal_levels() local
1739 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_enable_clock() local
1759 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_disable_clock() local
1775 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_is_clock_enabled() local
1792 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in icl_ddi_tc_get_pll() local
3129 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); in adlp_tbt_to_dp_alt_switch_wa() local
4274 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') argument
4348 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); in intel_ddi_init() local
4356 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); in intel_ddi_init()
[all …]
|
| A D | intel_dpll_mgr.h | 39 enum tc_port;
365 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
|
| A D | intel_display.h | 153 enum tc_port { enum
453 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
|
| A D | intel_display_power_well.c | 531 enum tc_port tc_port; in icl_tc_phy_aux_power_well_enable() local
533 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); in icl_tc_phy_aux_power_well_enable()
535 if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) & in icl_tc_phy_aux_power_well_enable()
|
| A D | intel_display.c | 2112 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) in intel_port_to_tc()
|
| /linux-6.3-rc2/drivers/gpu/drm/i915/ |
| A D | i915_reg.h | 7175 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ argument
7176 (tc_port) + 12 : \
7177 (tc_port) - TC_PORT_4 + 21))
7250 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ argument
7261 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ argument
|