| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_dpp_cm.c | 50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
214 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
216 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
270 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
278 reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B; in dpp1_cm_get_reg_field()
297 reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_degamma_reg_field()
470 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp1_program_input_csc()
472 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; in dpp1_program_input_csc()
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| A D | dcn10_dpp.c | 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
509 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) in dpp1_dppclk_control()
564 const struct dcn_dpp_mask *tf_mask) in dpp1_construct() argument
574 dpp->tf_mask = tf_mask; in dpp1_construct()
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| A D | dcn10_dpp_dscl.c | 54 dpp->tf_shift->field_name, dpp->tf_mask->field_name
368 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT, in dpp1_dscl_set_scl_filter()
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| A D | dcn10_resource.c | 362 static const struct dcn_dpp_mask tf_mask = { variable
588 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
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| A D | dcn10_dpp.h | 1357 const struct dcn_dpp_mask *tf_mask; member
1519 const struct dcn_dpp_mask *tf_mask);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_dpp_cm.c | 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
177 reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
179 reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
182 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
186 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
191 reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
193 reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
195 reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
199 reg->masks.exp_region_start = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_B; in dpp3_gamcor_reg_field()
345 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
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| A D | dcn30_dpp.c | 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
101 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11; in dpp3_program_post_csc()
103 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12; in dpp3_program_post_csc()
635 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
639 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
644 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn3_dpp_cm_get_reg_field()
646 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn3_dpp_cm_get_reg_field()
648 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn3_dpp_cm_get_reg_field()
652 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; in dcn3_dpp_cm_get_reg_field()
1473 const struct dcn3_dpp_mask *tf_mask) in dpp3_construct() argument
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| A D | dcn30_dpp.h | 563 const struct dcn3_dpp_mask *tf_mask; member
582 const struct dcn3_dpp_mask *tf_mask);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn32/ |
| A D | dcn32_dpp.c | 151 const struct dcn3_dpp_mask *tf_mask) in dpp32_construct() argument
161 dpp->tf_mask = tf_mask; in dpp32_construct()
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| A D | dcn32_dpp.h | 36 const struct dcn3_dpp_mask *tf_mask);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dpp_cm.c | 47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
192 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
285 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp2_program_input_csc()
287 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; in dpp2_program_input_csc()
363 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
367 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
372 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
374 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
376 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field()
[all …]
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| A D | dcn20_dpp.c | 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
409 const struct dcn2_dpp_mask *tf_mask) in dpp2_construct() argument
419 dpp->tf_mask = tf_mask; in dpp2_construct()
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| A D | dcn20_dpp.h | 683 const struct dcn2_dpp_mask *tf_mask; member
773 const struct dcn2_dpp_mask *tf_mask);
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_dpp.h | 62 const struct dcn201_dpp_mask *tf_mask; member
81 const struct dcn201_dpp_mask *tf_mask);
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| A D | dcn201_dpp.c | 42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
298 const struct dcn201_dpp_mask *tf_mask) in dpp201_construct() argument
308 dpp->tf_mask = tf_mask; in dpp201_construct()
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| A D | dcn201_resource.c | 479 static const struct dcn201_dpp_mask tf_mask = { variable
637 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn201_dpp_create()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn303/ |
| A D | dcn303_resource.c | 509 static const struct dcn3_dpp_mask tf_mask = { variable
520 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn302/ |
| A D | dcn302_resource.c | 549 static const struct dcn3_dpp_mask tf_mask = { variable
560 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 447 static const struct dcn2_dpp_mask tf_mask = { variable
510 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_resource.c | 417 static const struct dcn3_dpp_mask tf_mask = { variable
739 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn301_dpp_create()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn316/ |
| A D | dcn316_resource.c | 487 static const struct dcn3_dpp_mask tf_mask = { variable
936 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn314/ |
| A D | dcn314_resource.c | 512 static const struct dcn3_dpp_mask tf_mask = { variable
973 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn315/ |
| A D | dcn315_resource.c | 491 static const struct dcn3_dpp_mask tf_mask = { variable
937 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn321/ |
| A D | dcn321_resource.c | 372 static const struct dcn3_dpp_mask tf_mask = { variable
943 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn321_dpp_create()
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| /linux-6.3-rc2/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.c | 490 static const struct dcn3_dpp_mask tf_mask = { variable
941 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn31_dpp_create()
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