Searched refs:vdsc_cfg (Results 1 – 7 of 7) sorted by relevance
293 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { in drm_dsc_compute_rc_parameters()299 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()308 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * in drm_dsc_compute_rc_parameters()326 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; in drm_dsc_compute_rc_parameters()342 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()346 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { in drm_dsc_compute_rc_parameters()352 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); in drm_dsc_compute_rc_parameters()368 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()398 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()404 vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; in drm_dsc_compute_rc_parameters()[all …]
396 if (vdsc_cfg->slice_height >= 8) in calculate_rc_params()461 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()465 vdsc_cfg->simple_422 = false; in intel_dsc_compute_params()467 vdsc_cfg->vbr_enable = false; in intel_dsc_compute_params()543 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / in intel_dsc_compute_params()544 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()601 if (vdsc_cfg->convert_rgb) in intel_dsc_pps_configure()603 if (vdsc_cfg->simple_422) in intel_dsc_pps_configure()605 if (vdsc_cfg->vbr_enable) in intel_dsc_pps_configure()885 vdsc_cfg->slice_width) | in intel_dsc_pps_configure()[all …]
1613 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config() local1629 vdsc_cfg->convert_rgb = true; in gen11_dsi_dsc_compute_config()1632 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in gen11_dsi_dsc_compute_config()1634 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in gen11_dsi_dsc_compute_config()1641 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()1642 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()1644 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()1645 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()1647 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()1649 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); in gen11_dsi_dsc_compute_config()
1433 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in intel_dp_dsc_compute_params()1441 if (vdsc_cfg->pic_height % 8 == 0) in intel_dp_dsc_compute_params()1442 vdsc_cfg->slice_height = 8; in intel_dp_dsc_compute_params()1443 else if (vdsc_cfg->pic_height % 4 == 0) in intel_dp_dsc_compute_params()1444 vdsc_cfg->slice_height = 4; in intel_dp_dsc_compute_params()1446 vdsc_cfg->slice_height = 2; in intel_dp_dsc_compute_params()1452 vdsc_cfg->dsc_version_major = in intel_dp_dsc_compute_params()1455 vdsc_cfg->dsc_version_minor = in intel_dp_dsc_compute_params()1469 if (vdsc_cfg->dsc_version_minor == 2) in intel_dp_dsc_compute_params()1476 vdsc_cfg->block_pred_enable = in intel_dp_dsc_compute_params()[all …]
3490 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in fill_dsc() local3493 vdsc_cfg->dsc_version_major = dsc->version_major; in fill_dsc()3494 vdsc_cfg->dsc_version_minor = dsc->version_minor; in fill_dsc()3539 vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size, in fill_dsc()3543 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); in fill_dsc()3545 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; in fill_dsc()3547 vdsc_cfg->slice_height = dsc->slice_height; in fill_dsc()
782 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in psr2_granularity_check() local814 vdsc_cfg->slice_height % y_granularity) in psr2_granularity_check()1691 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_psr2_sel_fetch_pipe_alignment() local1697 y_alignment = vdsc_cfg->slice_height; in intel_psr2_sel_fetch_pipe_alignment()
17 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
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