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Searched refs:CLK_PLL1 (Results 1 – 5 of 5) sorted by relevance

/lk-master/platform/lpc43xx/
A Dinit.c55 writel(BASE_CLK_SEL(CLK_PLL1) | BASE_AUTOBLOCK, BASE_M4_CLK); in platform_early_init()
77 writel(IDIV_CLK_SEL(CLK_PLL1) | IDIV_N(2), IDIVE_CTRL); in platform_early_init()
87 __lpc43xx_main_clock_sel = CLK_PLL1; in platform_early_init()
/lk-master/platform/lpc43xx/include/platform/
A Dlpc43xx-clocks.h110 #define CLK_PLL1 0x09 macro
/lk-master/app/mdebug/
A Djtag.c71 writel(BASE_CLK_SEL(CLK_PLL1), BASE_PERIPH_CLK); in jtag_init()
A Dswd-m0sub.c98 writel(BASE_CLK_SEL(CLK_PLL1), BASE_PERIPH_CLK); in swd_init()
A Dswd-sgpio.c110 writel(BASE_CLK_SEL(CLK_PLL1), BASE_PERIPH_CLK); in sgpio_init()

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