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Searched refs:MODE (Results 1 – 25 of 97) sorted by relevance

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/lk-master/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Inc/
A Dstm32f7xx_hal_gpio.h286 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ argument
287 ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
288 ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
289 ((MODE) == GPIO_MODE_AF_PP) ||\
290 ((MODE) == GPIO_MODE_AF_OD) ||\
291 ((MODE) == GPIO_MODE_IT_RISING) ||\
292 ((MODE) == GPIO_MODE_IT_FALLING) ||\
293 ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
294 ((MODE) == GPIO_MODE_EVT_RISING) ||\
295 ((MODE) == GPIO_MODE_EVT_FALLING) ||\
[all …]
A Dstm32f7xx_hal_tim_ex.h462 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ argument
463 ((MODE) == TIM_OCMODE_PWM2) || \
467 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
469 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ argument
476 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
491 #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \ argument
516 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ argument
517 ((MODE) == TIM_SLAVEMODE_RESET) || \
518 ((MODE) == TIM_SLAVEMODE_GATED) || \
519 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
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A Dstm32f7xx_hal_dcmi_ex.h178 #define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \ argument
179 ((MODE) == DCMI_BSM_OTHER) || \
180 ((MODE) == DCMI_BSM_ALTERNATE_4) || \
181 ((MODE) == DCMI_BSM_ALTERNATE_2))
186 #define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \ argument
187 ((MODE) == DCMI_LSM_ALTERNATE_2))
A Dstm32f7xx_hal_qspi.h653 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ argument
654 ((MODE) == QSPI_DUALFLASH_DISABLE))
684 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ argument
689 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ argument
692 ((MODE) == QSPI_ADDRESS_4_LINES))
694 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ argument
699 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ argument
700 ((MODE) == QSPI_DATA_1_LINE) || \
702 ((MODE) == QSPI_DATA_4_LINES))
728 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ argument
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A Dstm32f7xx_hal_spi.h548 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ argument
549 ((MODE) == SPI_MODE_MASTER))
551 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ argument
552 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
553 ((MODE) == SPI_DIRECTION_1LINE))
555 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) argument
557 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ argument
558 ((MODE) == SPI_DIRECTION_1LINE))
599 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ argument
600 ((MODE) == SPI_TIMODE_ENABLE))
A Dstm32f7xx_hal_pwr.h388 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALL… argument
389 … ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
390 … ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
391 ((MODE) == PWR_PVD_MODE_NORMAL))
/lk-master/external/platform/stm32f0xx/STM32F0xx_HAL_Driver/inc/
A Dstm32f0xx_hal_crc_ex.h68 #define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ argument
69 ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
70 ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
71 ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
82 #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ argument
83 ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
A Dstm32f0xx_hal_smbus.h505 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ argument
506 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
529 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOS… argument
530 … ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
531 … ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
533 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) … argument
534 … ((MODE) == SMBUS_AUTOEND_MODE) || \
535 … ((MODE) == SMBUS_SOFTEND_MODE) || \
536 … ((MODE) == SMBUS_SENDPEC_MODE) || \
537 … ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
[all …]
A Dstm32f0xx_hal_spi.h549 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ argument
550 ((MODE) == SPI_MODE_MASTER))
552 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ argument
553 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
554 ((MODE) == SPI_DIRECTION_1LINE))
556 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) argument
558 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ argument
559 ((MODE) == SPI_DIRECTION_1LINE))
600 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ argument
601 ((MODE) == SPI_TIMODE_ENABLE))
/lk-master/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/inc/
A Dcrc_15xx.h48 __IO uint32_t MODE; /*!< CRC Mode Register */ member
113 LPC_CRC->MODE = (uint32_t) poly | flags; in Chip_CRC_SetPoly()
122 LPC_CRC->MODE = MODE_CFG_CRC16; in Chip_CRC_UseCRC16()
132 LPC_CRC->MODE = MODE_CFG_CRC32; in Chip_CRC_UseCRC32()
142 LPC_CRC->MODE = MODE_CFG_CCITT; in Chip_CRC_UseCCITT()
160 LPC_CRC->MODE = mode; in Chip_CRC_SetMode()
169 return LPC_CRC->MODE; in Chip_CRC_GetMode()
/lk-master/external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/inc/
A Dstm32f2xx_tim.h246 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ argument
251 ((MODE) == TIM_OCMode_PWM2))
252 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ argument
253 ((MODE) == TIM_OCMode_Active) || \
255 ((MODE) == TIM_OCMode_Toggle)|| \
256 ((MODE) == TIM_OCMode_PWM1) || \
257 ((MODE) == TIM_OCMode_PWM2) || \
270 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ argument
322 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ argument
782 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ argument
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A Dstm32f2xx_adc.h128 #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ argument
131 ((MODE) == ADC_DualMode_InjecSimult) || \
132 ((MODE) == ADC_DualMode_RegSimult) || \
133 ((MODE) == ADC_DualMode_Interl) || \
134 ((MODE) == ADC_DualMode_AlterTrig) || \
137 ((MODE) == ADC_TripleMode_InjecSimult) || \
138 ((MODE) == ADC_TripleMode_RegSimult) || \
139 ((MODE) == ADC_TripleMode_Interl) || \
140 ((MODE) == ADC_TripleMode_AlterTrig))
169 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ argument
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A Dstm32f2xx_spi.h134 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ argument
135 ((MODE) == SPI_Direction_2Lines_RxOnly) || \
136 ((MODE) == SPI_Direction_1Line_Rx) || \
137 ((MODE) == SPI_Direction_1Line_Tx))
148 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ argument
149 ((MODE) == SPI_Mode_Slave))
246 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ argument
247 ((MODE) == I2S_Mode_SlaveRx) || \
248 ((MODE) == I2S_Mode_MasterTx)|| \
249 ((MODE) == I2S_Mode_MasterRx))
A Dstm32f2xx_fsmc.h369 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ argument
370 ((MODE) == FSMC_WrapMode_Enable))
414 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ argument
415 ((MODE) == FSMC_ExtendedMode_Enable))
487 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ argument
488 ((MODE) == FSMC_AccessMode_B) || \
489 ((MODE) == FSMC_AccessMode_C) || \
490 ((MODE) == FSMC_AccessMode_D))
A Dstm32f2xx_can.h220 #define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ argument
221 ((MODE) == CAN_Mode_LoopBack)|| \
222 ((MODE) == CAN_Mode_Silent) || \
223 ((MODE) == CAN_Mode_Silent_LoopBack))
238 #define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ argument
239 ((MODE) == CAN_OperatingMode_Normal)|| \
240 ((MODE) == CAN_OperatingMode_Sleep))
334 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ argument
335 ((MODE) == CAN_FilterMode_IdList))
/lk-master/external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/inc/
A Dstm32f4xx_tim.h246 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ argument
251 ((MODE) == TIM_OCMode_PWM2))
252 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ argument
253 ((MODE) == TIM_OCMode_Active) || \
255 ((MODE) == TIM_OCMode_Toggle)|| \
256 ((MODE) == TIM_OCMode_PWM1) || \
257 ((MODE) == TIM_OCMode_PWM2) || \
270 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ argument
322 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ argument
782 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ argument
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A Dstm32f4xx_adc.h128 #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ argument
131 ((MODE) == ADC_DualMode_InjecSimult) || \
132 ((MODE) == ADC_DualMode_RegSimult) || \
133 ((MODE) == ADC_DualMode_Interl) || \
134 ((MODE) == ADC_DualMode_AlterTrig) || \
137 ((MODE) == ADC_TripleMode_InjecSimult) || \
138 ((MODE) == ADC_TripleMode_RegSimult) || \
139 ((MODE) == ADC_TripleMode_Interl) || \
140 ((MODE) == ADC_TripleMode_AlterTrig))
169 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ argument
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A Dstm32f4xx_spi.h155 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ argument
156 ((MODE) == SPI_Direction_2Lines_RxOnly) || \
157 ((MODE) == SPI_Direction_1Line_Rx) || \
158 ((MODE) == SPI_Direction_1Line_Tx))
169 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ argument
170 ((MODE) == SPI_Mode_Slave))
267 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ argument
268 ((MODE) == I2S_Mode_SlaveRx) || \
269 ((MODE) == I2S_Mode_MasterTx)|| \
270 ((MODE) == I2S_Mode_MasterRx))
A Dstm32f4xx_fmpi2c.h118 #define IS_FMPI2C_MODE(MODE) (((MODE) == FMPI2C_Mode_FMPI2C) || \ argument
119 ((MODE) == FMPI2C_Mode_SMBusDevice) || \
120 ((MODE) == FMPI2C_Mode_SMBusHost))
368 #define IS_RELOAD_END_MODE(MODE) (((MODE) == FMPI2C_Reload_Mode) || \ argument
369 ((MODE) == FMPI2C_AutoEnd_Mode) || \
370 ((MODE) == FMPI2C_SoftEnd_Mode))
387 #define IS_START_STOP_MODE(MODE) (((MODE) == FMPI2C_Generate_Stop) || \ argument
388 ((MODE) == FMPI2C_Generate_Start_Read) || \
389 ((MODE) == FMPI2C_Generate_Start_Write) || \
390 ((MODE) == FMPI2C_No_StartStop))
A Dstm32f4xx_sai.h180 #define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_Mode_MasterTx) || \ argument
181 ((MODE) == SAI_Mode_MasterRx) || \
182 ((MODE) == SAI_Mode_SlaveTx) || \
183 ((MODE) == SAI_Mode_SlaveRx))
414 #define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MonoMode) ||\ argument
415 ((MODE) == SAI_StreoMode))
459 #define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NoCompanding) || \ argument
460 ((MODE) == SAI_ULaw_1CPL_Companding) || \
461 ((MODE) == SAI_ALaw_1CPL_Companding) || \
462 ((MODE) == SAI_ULaw_2CPL_Companding) || \
[all …]
A Dstm32f4xx_fsmc.h369 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ argument
370 ((MODE) == FSMC_WrapMode_Enable))
414 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ argument
415 ((MODE) == FSMC_ExtendedMode_Enable))
487 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ argument
488 ((MODE) == FSMC_AccessMode_B) || \
489 ((MODE) == FSMC_AccessMode_C) || \
490 ((MODE) == FSMC_AccessMode_D))
/lk-master/external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/inc/
A Dstm32f10x_tim.h293 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ argument
298 ((MODE) == TIM_OCMode_PWM2))
299 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ argument
300 ((MODE) == TIM_OCMode_Active) || \
302 ((MODE) == TIM_OCMode_Toggle)|| \
303 ((MODE) == TIM_OCMode_PWM1) || \
304 ((MODE) == TIM_OCMode_PWM2) || \
317 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ argument
367 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ argument
829 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ argument
[all …]
A Dstm32f10x_spi.h131 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ argument
132 ((MODE) == SPI_Direction_2Lines_RxOnly) || \
133 ((MODE) == SPI_Direction_1Line_Rx) || \
134 ((MODE) == SPI_Direction_1Line_Tx))
145 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ argument
146 ((MODE) == SPI_Mode_Slave))
243 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ argument
244 ((MODE) == I2S_Mode_SlaveRx) || \
245 ((MODE) == I2S_Mode_MasterTx) || \
246 ((MODE) == I2S_Mode_MasterRx) )
A Dstm32f10x_cec.h71 #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ argument
72 ((MODE) == CEC_BitTimingErrFreeMode))
83 #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ argument
84 ((MODE) == CEC_BitPeriodFlexibleMode))
A Dstm32f10x_fsmc.h377 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ argument
378 ((MODE) == FSMC_WrapMode_Enable))
429 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ argument
430 ((MODE) == FSMC_ExtendedMode_Enable))
516 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ argument
517 ((MODE) == FSMC_AccessMode_B) || \
518 ((MODE) == FSMC_AccessMode_C) || \
519 ((MODE) == FSMC_AccessMode_D))

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