| /lk-master/external/platform/nrfx/mdk/ |
| A D | nrf52805.h | 135 #define __OM __O macro
224 …__OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power …
705 …__OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sing…
959 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be is…
1150 …__OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling …
1231 …__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the re…
1288 …__OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture …
1486 …__OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. T…
1654 …__OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for…
1658 …__OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register f…
[all …]
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| A D | nrf52811.h | 138 #define __OM __O macro
227 …__OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power …
772 …__OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sing…
780 …__OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessme…
1091 …__OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling …
1192 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be is…
1339 …__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the re…
1396 …__OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture …
1594 …__OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. …
1795 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on al…
[all …]
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| A D | nrf52820.h | 137 #define __OM __O macro
221 …__OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power …
782 …__OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sing…
790 …__OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessme…
1104 …__OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling …
1205 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be is…
1781 …__OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for…
1785 …__OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register f…
1789 …__OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a …
1850 …__OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the …
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| A D | nrf51.h | 129 #ifndef __OM /*!< Fallback for older CMSIS versions …
130 #define __OM __O macro
176 …__OM uint32_t EN; /*!< (@ 0x00000000) Enable channel group. …
177 …__OM uint32_t DIS; /*!< (@ 0x00000004) Disable channel group. …
330 …__OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one samp…
804 …__OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt. If a cr…
808 …__OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Stop current ECB encryption. If …
836 …__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based …
875 …__OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. …
877 …__OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encrypt/decrypt. This oper…
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| A D | nrf52810.h | 138 #define __OM __O macro
227 …__OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power …
753 …__OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sing…
998 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be is…
1190 …__OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling …
1234 …__OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for…
1271 …__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the re…
1328 …__OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture …
1526 …__OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. …
1727 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on al…
[all …]
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| A D | nrf52.h | 148 #define __OM __O macro
252 …__OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[0]: RAM0 pow…
254 …__OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[0]: RAM0 pow…
547 …__OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[0]: Enable c…
549 …__OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[0]: Disable …
890 …__OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sing…
1130 …__OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling …
1180 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be is…
1377 …__OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, cha…
1988 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on al…
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| A D | nrf52840.h | 154 #define __OM __O macro
272 …__OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power …
1097 …__OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sing…
1412 …__OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling …
1626 …__OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, cha…
2242 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on al…
2250 …__OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the curren…
2535 …__OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines in…
2633 …__OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external fla…
2635 …__OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM…
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| A D | nrf52833.h | 152 #define __OM __O macro
255 …__OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power …
1054 …__OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sing…
1386 …__OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling …
1600 …__OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, cha…
2221 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on al…
2229 …__OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the curren…
2340 …__OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for…
2344 …__OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register f…
2348 …__OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a …
[all …]
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| A D | nrf5340_application.h | 143 #define __OM __O macro
1419 …__OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK128M/HFCLK64M source …
1669 …__OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling …
2379 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on al…
2387 …__OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the curren…
2555 …__OM uint32_t TASKS_SEND[16]; /*!< (@ 0x00000000) Description collection: Trigger …
2594 …__OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external fla…
2596 …__OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM…
2661 …__OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, cha…
2878 …__OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the …
[all …]
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| A D | nrf5340_network.h | 122 #define __OM __O macro
601 …__OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK128M/HFCLK64M source …
746 …__OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sing…
754 …__OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessme…
951 …__OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for…
1051 …__OM uint32_t TASKS_CAPTURE[8]; /*!< (@ 0x00000040) Description collection: Capture …
1173 …__OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. T…
1307 …__OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Description collection: Capture …
1358 …__OM uint32_t TASKS_SEND[16]; /*!< (@ 0x00000000) Description collection: Trigger …
1474 …__OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling …
[all …]
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| A D | nrf9160.h | 145 #define __OM __O macro
690 …__OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power …
1031 …__OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling …
1088 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be is…
1319 …__OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for…
1367 …__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the re…
1437 …__OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture …
1621 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on al…
1629 …__OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the curren…
1737 …__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops M…
[all …]
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| /lk-master/external/arch/arm/arm-m/CMSIS/Include/ |
| A D | core_cm7.h | 246 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1042 __OM union
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
[all …]
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| A D | core_armv8mml.h | 287 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
538 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
542 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
543 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
544 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
545 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1016 __OM union
1018 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1019 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1020 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
[all …]
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| A D | core_cm33.h | 287 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
538 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
542 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
543 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
544 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
545 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1016 __OM union
1018 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1019 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1020 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
[all …]
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| A D | core_cm35p.h | 287 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
538 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
542 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
543 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
544 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
545 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1016 __OM union
1018 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1019 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1020 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
[all …]
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| A D | core_cm55.h | 294 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
546 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
550 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
551 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
552 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
553 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1077 __OM union
1079 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1080 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1081 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
[all …]
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| A D | core_armv81mml.h | 294 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
546 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
550 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
551 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
552 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
553 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
1077 __OM union
1079 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1080 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1081 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
[all …]
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| A D | core_cm3.h | 179 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
359 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…
760 __OM union
762 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
763 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
764 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
774 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1254 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
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| A D | core_sc300.h | 179 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
359 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…
745 __OM union
747 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
748 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
749 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
759 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1237 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
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| A D | core_cm4.h | 231 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
425 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…
818 __OM union
820 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
821 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
822 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
832 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1424 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
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| A D | core_armv8mbl.h | 202 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
740 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
994 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
1095 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
1206 …__OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register…
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| A D | core_cm23.h | 202 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
1069 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
1170 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
1281 …__OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register…
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| A D | core_cm0.h | 169 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
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| A D | core_cm1.h | 169 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
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| A D | core_sc000.h | 179 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
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