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Searched refs:ctrl (Results 1 – 25 of 28) sorted by relevance

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/lk-master/external/platform/pico/rp2_common/hardware_dma/
A Ddma.c45 uint32_t ctrl = channel->ctrl_trig; in print_dma_ctrl() local
48 (uint) ctrl, in print_dma_ctrl()
49 ctrl & DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS ? 1 : 0, in print_dma_ctrl()
50 ctrl & DMA_CH0_CTRL_TRIG_READ_ERROR_BITS ? 1 : 0, in print_dma_ctrl()
51 ctrl & DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS ? 1 : 0, in print_dma_ctrl()
52 ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS ? 1 : 0, in print_dma_ctrl()
55 ctrl & DMA_CH0_CTRL_TRIG_RING_SEL_BITS ? 1 : 0, in print_dma_ctrl()
57 ctrl & DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS ? 1 : 0, in print_dma_ctrl()
58 ctrl & DMA_CH0_CTRL_TRIG_INCR_READ_BITS ? 1 : 0, in print_dma_ctrl()
60 ctrl & DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS ? 1 : 0, in print_dma_ctrl()
[all …]
/lk-master/external/platform/pico/rp2_common/hardware_interp/include/hardware/
A Dinterp.h54 uint32_t ctrl; member
100 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SHIFT_BITS) | in interp_config_set_shift()
132 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS) | in interp_config_set_cross_input()
145 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS) | in interp_config_set_cross_result()
159 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SIGNED_BITS) | in interp_config_set_signed()
172 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS) | in interp_config_set_add_raw()
192 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_BLEND_BITS) | in interp_config_set_blend()
207 c->ctrl = (c->ctrl & ~SIO_INTERP1_CTRL_LANE0_CLAMP_BITS) | in interp_config_set_clamp()
225 c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS) | in interp_config_set_force_bits()
258 interp->ctrl[lane] = config->ctrl; in interp_set_config()
[all …]
/lk-master/external/platform/pico/rp2_common/hardware_dma/include/hardware/
A Ddma.h118 uint32_t ctrl; member
129 …c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_READ_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR… in channel_config_set_read_increment()
141 …c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INC… in channel_config_set_write_increment()
161 … c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB); in channel_config_set_dreq()
189 …c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (size << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB… in channel_config_set_transfer_data_size()
209 c->ctrl = (c->ctrl & ~(DMA_CH0_CTRL_TRIG_RING_SIZE_BITS | DMA_CH0_CTRL_TRIG_RING_SEL_BITS)) | in channel_config_set_ring()
224 …c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_B… in channel_config_set_bswap()
238 …c->ctrl = irq_quiet ? (c->ctrl | DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG… in channel_config_set_irq_quiet()
253 … c->ctrl = enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_EN_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_EN_BITS); in channel_config_set_enable()
265 c->ctrl = sniff_enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS) : (c->ctrl & in channel_config_set_sniff_enable()
[all …]
/lk-master/external/platform/pico/rp2_common/hardware_interp/
A Dinterp.c43 saver->ctrl[0] = interp->ctrl[0]; in interp_save()
44 saver->ctrl[1] = interp->ctrl[1]; in interp_save()
53 interp->ctrl[0] = saver->ctrl[0]; in interp_restore()
54 interp->ctrl[1] = saver->ctrl[1]; in interp_restore()
/lk-master/platform/zynq/
A Dgem.c63 uint32_t ctrl; member
151 uint32_t ctrl = gem.descs->tx_tbl[cur_pos].ctrl & TX_DESC_WRAP; /* protect the wrap bit */ in queue_pkts_in_tx_tbl() local
152 ctrl |= TX_BUF_LEN(p->dlen); in queue_pkts_in_tx_tbl()
156 ctrl |= TX_LAST_BUF; in queue_pkts_in_tx_tbl()
161 gem.descs->tx_tbl[cur_pos].ctrl = ctrl; in queue_pkts_in_tx_tbl()
300 gem.descs->rx_tbl[n].ctrl = 0; in gem_cfg_buffer_descs()
348 uint32_t ctrl = gem.descs->rx_tbl[bp].ctrl; in gem_rx_thread() local
351 p->dlen = RX_BUF_LEN(ctrl); in gem_rx_thread()
377 gem.descs->rx_tbl[bp].ctrl = 0; in gem_rx_thread()
585 uint32_t ctrl = gem.descs->tx_tbl[i].ctrl; in cmd_gem() local
[all …]
A Dclocks.c260 uint32_t ctrl = *REG32(clk_reg); in zynq_set_clock() local
263 ctrl = (ctrl & ~(0x3f << 20)) | (divisor2 << 20); in zynq_set_clock()
264 ctrl = (ctrl & ~(0x3f << 8)) | (divisor << 8); in zynq_set_clock()
265 ctrl = (ctrl & ~(0x3 << 4)) | (source << 4); in zynq_set_clock()
268 ctrl |= (1 << enable_bitpos); in zynq_set_clock()
270 *REG32(clk_reg) = ctrl; in zynq_set_clock()
274 uint32_t ctrl = *REG32(clk_reg); in zynq_set_clock() local
276 ctrl &= ~(1 << enable_bitpos); in zynq_set_clock()
278 *REG32(clk_reg) = ctrl; in zynq_set_clock()
/lk-master/external/platform/pico/rp2_common/hardware_watchdog/
A Dwatchdog.c31 return (watchdog_hw->ctrl & WATCHDOG_CTRL_TIME_BITS) / 2 ; in watchdog_get_count()
37 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in _watchdog_enable()
47 hw_set_bits(&watchdog_hw->ctrl, dbg_bits); in _watchdog_enable()
49 hw_clear_bits(&watchdog_hw->ctrl, dbg_bits); in _watchdog_enable()
63 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in _watchdog_enable()
78 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in watchdog_reboot()
/lk-master/external/platform/pico/rp2_common/hardware_clocks/
A Dclocks.c38 hw_clear_bits(&clock->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS); in clock_stop()
66 hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); in clock_configure()
74 hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); in clock_configure()
90 hw_write_masked(&clock->ctrl, in clock_configure()
96 hw_write_masked(&clock->ctrl, in clock_configure()
104 hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); in clock_configure()
131 clocks_hw->resus.ctrl = 0; in clocks_init()
137 hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); in clocks_init()
140 hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); in clocks_init()
313 clocks_hw->resus.ctrl = CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS | timeout; in clocks_enable_resus()
[all …]
/lk-master/external/platform/pico/rp2_common/hardware_xosc/
A Dxosc.c19 xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ; in xosc_init()
26 hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB); in xosc_init()
33 uint32_t tmp = xosc_hw->ctrl; in xosc_disable()
36 xosc_hw->ctrl = tmp; in xosc_disable()
/lk-master/external/platform/pico/rp2_common/hardware_gpio/
A Dgpio.c38 iobank0_hw->io[gpio].ctrl = fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB; in gpio_set_function()
44 …return (enum gpio_function) ((iobank0_hw->io[gpio].ctrl & IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS) >> IO_… in gpio_get_function()
61 hw_write_masked(&iobank0_hw->io[gpio].ctrl, in gpio_set_inover()
69 hw_write_masked(&iobank0_hw->io[gpio].ctrl, in gpio_set_outover()
77 hw_write_masked(&iobank0_hw->io[gpio].ctrl, in gpio_set_oeover()
/lk-master/external/platform/pico/rp2_common/pico_fix/rp2040_usb_device_enumeration/
A Drp2040_usb_device_enumeration.c93 gpio_ctrl_prev = iobank0_hw->io[dp].ctrl; in hw_enumeration_fix_force_ls_j()
102 hw_write_masked(&iobank0_hw->io[dp].ctrl, in hw_enumeration_fix_force_ls_j()
142 iobank0_hw->io[dp].ctrl = gpio_ctrl_prev; in hw_enumeration_fix_finish()
/lk-master/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/src/
A Dclock_15xx.c386 uint32_t ctrl = 0; in Chip_Clock_SetPLLBypass() local
389 ctrl |= (1 << 0); in Chip_Clock_SetPLLBypass()
392 ctrl |= (1 << 1); in Chip_Clock_SetPLLBypass()
395 LPC_SYSCTL->SYSOSCCTRL = ctrl; in Chip_Clock_SetPLLBypass()
/lk-master/external/platform/pico/rp2_common/hardware_rtc/
A Drtc.c19 return (rtc_hw->ctrl & RTC_CTRL_RTC_ACTIVE_BITS); in rtc_running()
61 rtc_hw->ctrl = 0; in rtc_set_datetime()
77 rtc_hw->ctrl = RTC_CTRL_LOAD_BITS; in rtc_set_datetime()
80 rtc_hw->ctrl = RTC_CTRL_RTC_ENABLE_BITS; in rtc_set_datetime()
/lk-master/external/platform/pico/rp2040/hardware_structs/include/hardware/structs/
A Dclocks.h35 io_rw_32 ctrl; member
55 io_rw_32 ctrl; member
A Dusb.h89 io_rw_32 ctrl; member
98 io_rw_32 ctrl; member
A Dioqspi.h17 io_rw_32 ctrl; member
A Dwatchdog.h15 io_rw_32 ctrl; member
A Dmpu.h15 io_rw_32 ctrl; member
A Dxosc.h16 io_rw_32 ctrl; member
A Dxip_ctrl.h13 io_rw_32 ctrl; member
A Dinterp.h19 io_rw_32 ctrl[2]; member
A Drosc.h15 io_rw_32 ctrl; member
A Diobank0.h24 io_rw_32 ctrl; member
/lk-master/external/platform/pico/rp2_common/hardware_pio/include/hardware/
A Dpio.h506 pio->ctrl = (pio->ctrl & ~(1u << sm)) | (!!enabled << sm); in pio_sm_set_enabled()
523 pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u); in pio_set_sm_mask_enabled()
536 pio->ctrl |= 1u << (PIO_CTRL_SM_RESTART_LSB + sm); in pio_sm_restart()
549 pio->ctrl |= (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS; in pio_restart_sm_mask()
559 pio->ctrl |= 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm); in pio_sm_clkdiv_restart()
572 pio->ctrl |= (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS; in pio_clkdiv_restart_sm_mask()
582 pio->ctrl |= ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | in pio_enable_sm_mask_in_sync()
/lk-master/external/platform/pico/rp2_common/pico_runtime/
A Druntime.c42 if (mpu_hw->ctrl) { in runtime_install_stack_guard()
54 mpu_hw->ctrl = 5; // enable mpu with background default map in runtime_install_stack_guard()

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