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/lk-master/external/platform/nrfx/hal/
A Dnrf_regulators.h138 NRF_STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bool enable);
173 bool enable,
219 NRF_STATIC_INLINE void nrf_regulators_dcdcen_vddh_set(NRF_REGULATORS_Type * p_reg, bool enable);
234 NRF_STATIC_INLINE void nrf_regulators_dcdcen_set(NRF_REGULATORS_Type * p_reg, bool enable) in nrf_regulators_dcdcen_set() argument
237 p_reg->DCDCEN = (enable ? REGULATORS_DCDCEN_DCDCEN_Msk : 0); in nrf_regulators_dcdcen_set()
239 p_reg->VREGMAIN.DCDCEN = (enable ? REGULATORS_VREGMAIN_DCDCEN_DCDCEN_Msk : 0); in nrf_regulators_dcdcen_set()
265 bool enable, in nrf_regulators_pofcon_set() argument
276 (enable ? in nrf_regulators_pofcon_set()
319 NRF_STATIC_INLINE void nrf_regulators_dcdcen_vddh_set(NRF_REGULATORS_Type * p_reg, bool enable) in nrf_regulators_dcdcen_vddh_set() argument
321 p_reg->VREGH.DCDCEN = (enable) ? REGULATORS_VREGH_DCDCEN_DCDCEN_Enabled : in nrf_regulators_dcdcen_vddh_set()
[all …]
A Dnrf_oscillators.h64 NRF_STATIC_INLINE void nrf_oscillators_lfxo_bypass_set(NRF_OSCILLATORS_Type * p_reg, bool enable);
88 bool enable,
92 NRF_STATIC_INLINE void nrf_oscillators_lfxo_bypass_set(NRF_OSCILLATORS_Type * p_reg, bool enable) in nrf_oscillators_lfxo_bypass_set() argument
94 p_reg->XOSC32KI.BYPASS = (enable ? OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Enabled : in nrf_oscillators_lfxo_bypass_set()
105 bool enable, in nrf_oscillators_hfxo_cap_set() argument
109 (enable ? ((OSCILLATORS_XOSC32MCAPS_ENABLE_Enabled << OSCILLATORS_XOSC32MCAPS_ENABLE_Pos) | in nrf_oscillators_hfxo_cap_set()
A Dnrf_cache.h106 NRF_STATIC_INLINE void nrf_cache_profiling_set(NRF_CACHE_Type * p_reg, bool enable);
188 NRF_STATIC_INLINE void nrf_cache_ram_mode_set(NRF_CACHE_Type * p_reg, bool enable);
213 NRF_STATIC_INLINE void nrf_cache_update_lock_set(NRF_CACHE_Type * p_reg, bool enable);
305 NRF_STATIC_INLINE void nrf_cache_profiling_set(NRF_CACHE_Type * p_reg, bool enable) in nrf_cache_profiling_set() argument
308 (enable ? CACHE_PROFILINGENABLE_ENABLE_Enable : CACHE_PROFILINGENABLE_ENABLE_Disable); in nrf_cache_profiling_set()
340 NRF_STATIC_INLINE void nrf_cache_ram_mode_set(NRF_CACHE_Type * p_reg, bool enable) in nrf_cache_ram_mode_set() argument
342 p_reg->MODE = (enable ? CACHE_MODE_MODE_Ram : CACHE_MODE_MODE_Cache); in nrf_cache_ram_mode_set()
350 NRF_STATIC_INLINE void nrf_cache_update_lock_set(NRF_CACHE_Type * p_reg, bool enable) in nrf_cache_update_lock_set() argument
353 (enable ? CACHE_WRITELOCK_WRITELOCK_Locked : CACHE_WRITELOCK_WRITELOCK_Unlocked); in nrf_cache_update_lock_set()
A Dnrf_vreqctrl.h54 NRF_STATIC_INLINE void nrf_vreqctrl_radio_high_voltage_set(NRF_VREQCTRL_Type * p_reg, bool enable);
68 NRF_STATIC_INLINE void nrf_vreqctrl_radio_high_voltage_set(NRF_VREQCTRL_Type * p_reg, bool enable) in nrf_vreqctrl_radio_high_voltage_set() argument
71 (enable ? VREQCTRL_VREGRADIO_VREQH_VREQH_Enabled : VREQCTRL_VREGRADIO_VREQH_VREQH_Disabled); in nrf_vreqctrl_radio_high_voltage_set()
A Dnrf_bprot.h73 bool enable);
110 bool enable) in nrf_bprot_nvm_protection_in_debug_set() argument
113 (enable ? 0 : BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk); in nrf_bprot_nvm_protection_in_debug_set()
A Dnrf_mpu.h119 bool enable);
161 bool enable) in nrf_mpu_nvm_protection_in_debug_set() argument
164 (enable ? 0 : MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk); in nrf_mpu_nvm_protection_in_debug_set()
A Dnrf_power.h620 bool enable,
728 NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable);
797 NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable);
996 bool enable, in nrf_power_pofcon_set() argument
1008 (enable ? in nrf_power_pofcon_set()
1112 NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable) in nrf_power_dcdcen_set() argument
1114 p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) << in nrf_power_dcdcen_set()
1148 NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable) in nrf_power_dcdcen_vddh_set() argument
1155 p_reg->DCDCEN0 = (enable ? POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) << in nrf_power_dcdcen_vddh_set()
A Dnrf_qspi.h586 NRF_STATIC_INLINE void nrf_qspi_xip_set(NRF_QSPI_Type * p_reg, bool enable);
605 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg, bool enable);
624 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool enable);
910 NRF_STATIC_INLINE void nrf_qspi_xip_set(NRF_QSPI_Type * p_reg, bool enable) in nrf_qspi_xip_set() argument
912 p_reg->XIPEN = (enable ? QSPI_XIPEN_XIPEN_Enable << QSPI_XIPEN_XIPEN_Pos in nrf_qspi_xip_set()
930 NRF_STATIC_INLINE void nrf_qspi_xip_encryption_set(NRF_QSPI_Type * p_reg, bool enable) in nrf_qspi_xip_encryption_set() argument
933 (enable ? QSPI_XIP_ENC_ENABLE_ENABLE_Enabled << QSPI_XIP_ENC_ENABLE_ENABLE_Pos in nrf_qspi_xip_encryption_set()
951 NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool enable) in nrf_qspi_dma_encryption_set() argument
954 (enable ? QSPI_DMA_ENC_ENABLE_ENABLE_Enabled << QSPI_DMA_ENC_ENABLE_ENABLE_Pos in nrf_qspi_dma_encryption_set()
/lk-master/platform/pc/
A Dinterrupts.c70 static void enable(unsigned int vector, bool enable) { in enable() argument
76 if (enable && (irqMask[0] & bit)) { in enable()
81 } else if (!enable && !(irqMask[0] & bit)) { in enable()
92 if (enable && (irqMask[1] & bit)) { in enable()
97 } else if (!enable && !(irqMask[1] & bit)) { in enable()
145 enable(vector, false); in mask_interrupt()
173 enable(vector, true); in unmask_interrupt()
/lk-master/platform/qemu-mips/
A Dintc.c91 static void enable(unsigned int vector, bool enable) { in enable() argument
95 if (enable && (irqMask[0] & bit)) { in enable()
100 } else if (!enable && !(irqMask[0] & bit)) { in enable()
111 if (enable && (irqMask[1] & bit)) { in enable()
116 } else if (!enable && !(irqMask[1] & bit)) { in enable()
181 enable(vector, false); in mask_interrupt()
208 enable(vector, true); in unmask_interrupt()
/lk-master/external/platform/pico/rp2_common/hardware_i2c/
A Di2c.c12 check_hw_layout(i2c_hw_t, enable, I2C_IC_ENABLE_OFFSET);
39 i2c->hw->enable = 0; in i2c_init()
78 i2c->hw->enable = 0; in i2c_set_baudrate()
88 i2c->hw->enable = 1; in i2c_set_baudrate()
95 i2c->hw->enable = 0; in i2c_set_slave_mode()
108 i2c->hw->enable = 1; in i2c_set_slave_mode()
119 i2c->hw->enable = 0; in i2c_write_blocking_internal()
121 i2c->hw->enable = 1; in i2c_write_blocking_internal()
207 i2c->hw->enable = 0; in i2c_read_blocking_internal()
209 i2c->hw->enable = 1; in i2c_read_blocking_internal()
/lk-master/dev/interrupt/arm_gic/
A Darm_gic.c158 static void gic_set_enable(uint vector, bool enable) { in gic_set_enable() argument
162 if (enable) in gic_set_enable()
506 bool enable = args->params[1]; in smc_intc_request_fiq() local
509 dprintf(SPEW, "%s: fiq %d, enable %d\n", __func__, fiq, enable); in smc_intc_request_fiq()
516 gic_set_enable(fiq, enable); in smc_intc_request_fiq()
517 bitmap_update_locked(enabled_fiq_mask, fiq, enable); in smc_intc_request_fiq()
519 dprintf(SPEW, "%s: fiq %d, enable %d done\n", __func__, fiq, enable); in smc_intc_request_fiq()
528 static bool update_fiq_targets(u_int cpu, bool enable, u_int triggered_fiq, bool resume_gicd) { in update_fiq_targets() argument
544 LTRACEF("cpu %d, irq %i, enable %d\n", cpu, fiq, enable); in update_fiq_targets()
546 arm_gic_set_target_locked(fiq, 1U << cpu, enable ? ~0 : 0); in update_fiq_targets()
[all …]
/lk-master/platform/stm32f0xx/
A Drcc.c38 void stm32_rcc_set_enable(stm32_rcc_clk_t clock, bool enable) { in stm32_rcc_set_enable() argument
40 if (enable) { in stm32_rcc_set_enable()
/lk-master/dev/cache/pl310/
A Dpl310.c103 status_t pl310_set_enable(bool enable) { in pl310_set_enable() argument
104 LTRACEF("enable %d\n", enable); in pl310_set_enable()
106 if (enable) { in pl310_set_enable()
/lk-master/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/src/
A Dswm_15xx.c88 void Chip_SWM_FixedPinEnable(CHIP_SWM_PIN_FIXED_T pin, bool enable) in Chip_SWM_FixedPinEnable() argument
90 if (enable) { in Chip_SWM_FixedPinEnable()
/lk-master/arch/arm/arm/
A Dfpu.c36 void arm_fpu_set_enable(bool enable) { in arm_fpu_set_enable() argument
38 write_fpexc(enable ? (1<<30) : 0); in arm_fpu_set_enable()
/lk-master/external/platform/pico/rp2_common/hardware_adc/include/hardware/
A Dadc.h110 static inline void adc_set_temp_sensor_enabled(bool enable) { in adc_set_temp_sensor_enabled() argument
111 if (enable) in adc_set_temp_sensor_enabled()
/lk-master/platform/zynq/
A Dclocks.c245 status_t zynq_set_clock(enum zynq_periph periph, bool enable, enum zynq_clock_source source, uint32… in zynq_set_clock() argument
247 DEBUG_ASSERT(!enable || (divisor > 0 && divisor <= 0x3f)); in zynq_set_clock()
259 if (enable) { in zynq_set_clock()
/lk-master/external/platform/pico/rp2_common/pico_stdio/
A Dstdio.c159 void stdio_set_driver_enabled(stdio_driver_t *driver, bool enable) { in stdio_set_driver_enabled() argument
163 if (!enable) { in stdio_set_driver_enabled()
171 if (enable) { in stdio_set_driver_enabled()
/lk-master/dev/cache/pl310/include/dev/cache/
A Dpl310.h13 status_t pl310_set_enable(bool enable);
/lk-master/external/lib/lwip/core/snmp/
A Dmsg_out.c60 u8_t enable; member
81 snmp_trap_dst_enable(u8_t dst_idx, u8_t enable) in snmp_trap_dst_enable() argument
85 trap_dst[dst_idx].enable = enable; in snmp_trap_dst_enable()
223 if ((td->enable != 0) && !ip_addr_isany(&td->dip)) in snmp_send_trap()
292 u8_t enable; in snmp_authfail_trap() local
293 snmp_get_snmpenableauthentraps(&enable); in snmp_authfail_trap()
294 if (enable == 1) in snmp_authfail_trap()
/lk-master/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/inc/usbd/
A Dusbd_hw.h413 …orCode_t (*EnableEvent)(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t enable);
449 …ode_t hwUSB_EnableEvent(USBD_HANDLE_T hUsb, uint32_t EPNum, uint32_t event_type, uint32_t enable);
/lk-master/dev/include/dev/
A Ddisplay.h18 int display_enable(bool enable);
/lk-master/external/platform/pico/rp2040/hardware_structs/include/hardware/structs/
A Di2c.h40 io_rw_32 enable; member
/lk-master/platform/stm32f0xx/include/platform/
A Drcc.h81 void stm32_rcc_set_enable(stm32_rcc_clk_t clock, bool enable);

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