fpga0_clk (reference) in projects: lk-master

Searched refs:fpga0_clk (Results 1 – 4 of 4) sorted by relevance

/lk-master/target/uzed/
A D	target.c	`154 .fpga0_clk = CLK_CTRL_DIVISOR0(10) \| CLK_CTRL_DIVISOR1(1),`
/lk-master/target/zybo/
A D	target.c	`158 .fpga0_clk = CLK_CTRL_DIVISOR0(10) \| CLK_CTRL_DIVISOR1(1),`
/lk-master/platform/zynq/
A D	platform.c	`144 SLCR_REG(FPGA0_CLK_CTRL) = zynq_clk_cfg.fpga0_clk; in zynq_clk_init()`
/lk-master/platform/zynq/include/platform/
A D	zynq.h	`132 uint32_t fpga0_clk; member`

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