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Searched refs:fpga1_clk (Results 1 – 4 of 4) sorted by relevance

/lk-master/target/uzed/
A Dtarget.c155 .fpga1_clk = CLK_CTRL_DIVISOR0(10) | CLK_CTRL_DIVISOR1(1),
/lk-master/target/zybo/
A Dtarget.c159 .fpga1_clk = CLK_CTRL_SRCSEL(3) | CLK_CTRL_DIVISOR0(6) | CLK_CTRL_DIVISOR1(1),
/lk-master/platform/zynq/
A Dplatform.c145 SLCR_REG(FPGA1_CLK_CTRL) = zynq_clk_cfg.fpga1_clk; in zynq_clk_init()
/lk-master/platform/zynq/include/platform/
A Dzynq.h133 uint32_t fpga1_clk; member

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