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Searched refs:mask (Results 1 – 25 of 150) sorted by relevance

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/lk-master/platform/mediatek/mt6735/
A Dinterrupts.c216 unsigned int mask = 1 << (irq % 32); in mt_irq_mask() local
227 unsigned int mask = 1 << (irq % 32); in mt_irq_unmask() local
248 if (mask) { in mt_irq_mask_all()
270 mask->header = IRQ_MASK_HEADER; in mt_irq_mask_all()
271 mask->footer = IRQ_MASK_FOOTER; in mt_irq_mask_all()
285 if (!mask) { in mt_irq_mask_restore()
288 if (mask->header != IRQ_MASK_HEADER) { in mt_irq_mask_restore()
291 if (mask->footer != IRQ_MASK_FOOTER) { in mt_irq_mask_restore()
295 DRV_WriteReg32(GIC_ICDISER0,mask->mask0); in mt_irq_mask_restore()
296 DRV_WriteReg32(GIC_ICDISER1,mask->mask1); in mt_irq_mask_restore()
[all …]
/lk-master/external/platform/pico/rp2_common/hardware_gpio/include/hardware/
A Dgpio.h352 sio_hw->gpio_set = mask; in gpio_set_mask()
361 sio_hw->gpio_clr = mask; in gpio_clr_mask()
370 sio_hw->gpio_togl = mask; in gpio_xor_mask()
404 uint32_t mask = 1ul << gpio; in gpio_put() local
406 gpio_set_mask(mask); in gpio_put()
408 gpio_clr_mask(mask); in gpio_put()
423 sio_hw->gpio_oe_set = mask; in gpio_set_dir_out_masked()
432 sio_hw->gpio_oe_clr = mask; in gpio_set_dir_in_masked()
466 uint32_t mask = 1ul << gpio; in gpio_set_dir() local
468 gpio_set_dir_out_masked(mask); in gpio_set_dir()
[all …]
/lk-master/external/arch/arm/arm-m/CMSIS/Include/
A Dpmu_armv8.h181 __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
182 __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
244 __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) in ARM_PMU_CNTR_Enable() argument
246 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
256 __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) in ARM_PMU_CNTR_Disable() argument
258 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
298 __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) in ARM_PMU_Set_CNTR_OVS() argument
300 PMU->OVSCLR = mask; in ARM_PMU_Set_CNTR_OVS()
312 PMU->INTENSET = mask; in ARM_PMU_Set_CNTR_IRQ_Enable()
324 PMU->INTENCLR = mask; in ARM_PMU_Set_CNTR_IRQ_Disable()
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/lk-master/external/platform/nrfx/hal/
A Dnrf_rng.h80 NRF_STATIC_INLINE void nrf_rng_int_enable(NRF_RNG_Type * p_reg, uint32_t mask);
88 NRF_STATIC_INLINE void nrf_rng_int_disable(NRF_RNG_Type * p_reg, uint32_t mask);
159 NRF_STATIC_INLINE void nrf_rng_shorts_enable(NRF_RNG_Type * p_reg, uint32_t mask);
195 NRF_STATIC_INLINE void nrf_rng_int_enable(NRF_RNG_Type * p_reg, uint32_t mask) in nrf_rng_int_enable() argument
197 p_reg->INTENSET = mask; in nrf_rng_int_enable()
200 NRF_STATIC_INLINE void nrf_rng_int_disable(NRF_RNG_Type * p_reg, uint32_t mask) in nrf_rng_int_disable() argument
202 p_reg->INTENCLR = mask; in nrf_rng_int_disable()
207 return p_reg->INTENSET & mask; in nrf_rng_int_enable_check()
238 NRF_STATIC_INLINE void nrf_rng_shorts_enable(NRF_RNG_Type * p_reg, uint32_t mask) in nrf_rng_shorts_enable() argument
240 p_reg->SHORTS |= mask; in nrf_rng_shorts_enable()
[all …]
A Dnrf_usbreg.h99 NRF_STATIC_INLINE void nrf_usbreg_int_enable(NRF_USBREG_Type * p_reg, uint32_t mask);
107 NRF_STATIC_INLINE void nrf_usbreg_int_disable(NRF_USBREG_Type * p_reg, uint32_t mask);
118 uint32_t mask);
144 NRF_STATIC_INLINE void nrf_usbreg_int_enable(NRF_USBREG_Type * p_reg, uint32_t mask) in nrf_usbreg_int_enable() argument
146 p_reg->INTENSET = mask; in nrf_usbreg_int_enable()
149 NRF_STATIC_INLINE void nrf_usbreg_int_disable(NRF_USBREG_Type * p_reg, uint32_t mask) in nrf_usbreg_int_disable() argument
151 p_reg->INTENCLR = mask; in nrf_usbreg_int_disable()
155 uint32_t mask) in nrf_usbreg_int_enable_check() argument
157 return p_reg->INTENSET & mask; in nrf_usbreg_int_enable_check()
A Dnrf_fpu.h99 NRF_STATIC_INLINE void nrf_fpu_int_enable(NRF_FPU_Type * p_reg, uint32_t mask);
107 NRF_STATIC_INLINE void nrf_fpu_int_disable(NRF_FPU_Type * p_reg, uint32_t mask);
117 NRF_STATIC_INLINE uint32_t nrf_fpu_int_enable_check(NRF_FPU_Type const * p_reg, uint32_t mask);
133 NRF_STATIC_INLINE void nrf_fpu_int_enable(NRF_FPU_Type * p_reg, uint32_t mask) in nrf_fpu_int_enable() argument
135 p_reg->INTENSET = mask; in nrf_fpu_int_enable()
138 NRF_STATIC_INLINE void nrf_fpu_int_disable(NRF_FPU_Type * p_reg, uint32_t mask) in nrf_fpu_int_disable() argument
140 p_reg->INTENCLR = mask; in nrf_fpu_int_disable()
143 NRF_STATIC_INLINE uint32_t nrf_fpu_int_enable_check(NRF_FPU_Type const * p_reg, uint32_t mask) in nrf_fpu_int_enable_check() argument
145 return p_reg->INTENSET & mask; in nrf_fpu_int_enable_check()
A Dnrf_dcnf.h71 uint32_t mask);
98 uint32_t mask);
125 uint32_t mask);
150 uint32_t mask) in nrf_dcnf_peripheral_access_set() argument
152 p_reg->EXTPERI[port_idx].PROTECT = mask; in nrf_dcnf_peripheral_access_set()
165 uint32_t mask) in nrf_dcnf_ram_access_set() argument
167 p_reg->EXTRAM[port_idx].PROTECT = mask; in nrf_dcnf_ram_access_set()
180 uint32_t mask) in nrf_dcnf_code_access_set() argument
182 p_reg->EXTCODE[port_idx].PROTECT = mask; in nrf_dcnf_code_access_set()
A Dnrf_twi.h191 uint32_t mask);
307 uint32_t mask);
345 p_reg->SHORTS |= mask; in nrf_twi_shorts_enable()
351 p_reg->SHORTS &= ~(mask); in nrf_twi_shorts_disable()
355 uint32_t mask) in nrf_twi_int_enable() argument
357 p_reg->INTENSET = mask; in nrf_twi_int_enable()
361 uint32_t mask) in nrf_twi_int_disable() argument
363 p_reg->INTENCLR = mask; in nrf_twi_int_disable()
368 return p_reg->INTENSET & mask; in nrf_twi_int_enable_check()
448 uint32_t mask) in nrf_twi_shorts_set() argument
[all …]
A Dnrf_mwu.h137 NRF_STATIC_INLINE void nrf_mwu_int_enable(NRF_MWU_Type * p_reg, uint32_t mask);
155 NRF_STATIC_INLINE void nrf_mwu_int_disable(NRF_MWU_Type * p_reg, uint32_t mask);
163 NRF_STATIC_INLINE void nrf_mwu_nmi_enable(NRF_MWU_Type * p_reg, uint32_t mask);
299 NRF_STATIC_INLINE void nrf_mwu_int_enable(NRF_MWU_Type * p_reg, uint32_t mask) in nrf_mwu_int_enable() argument
301 p_reg->INTENSET = mask; in nrf_mwu_int_enable()
306 return p_reg->INTENSET & mask; in nrf_mwu_int_enable_check()
311 p_reg->INTENCLR = mask; in nrf_mwu_int_disable()
314 NRF_STATIC_INLINE void nrf_mwu_nmi_enable(NRF_MWU_Type * p_reg, uint32_t mask) in nrf_mwu_nmi_enable() argument
316 p_reg->NMIENSET = mask; in nrf_mwu_nmi_enable()
321 return p_reg->NMIENSET & mask; in nrf_mwu_nmi_enable_check()
[all …]
A Dnrf_temp.h73 NRF_STATIC_INLINE void nrf_temp_int_enable(NRF_TEMP_Type * p_reg, uint32_t mask);
81 NRF_STATIC_INLINE void nrf_temp_int_disable(NRF_TEMP_Type * p_reg, uint32_t mask);
91 NRF_STATIC_INLINE uint32_t nrf_temp_int_enable_check(NRF_TEMP_Type const * p_reg, uint32_t mask);
155 NRF_STATIC_INLINE void nrf_temp_int_enable(NRF_TEMP_Type * p_reg, uint32_t mask) in nrf_temp_int_enable() argument
157 p_reg->INTENSET = mask; in nrf_temp_int_enable()
160 NRF_STATIC_INLINE void nrf_temp_int_disable(NRF_TEMP_Type * p_reg, uint32_t mask) in nrf_temp_int_disable() argument
162 p_reg->INTENCLR = mask; in nrf_temp_int_disable()
165 NRF_STATIC_INLINE uint32_t nrf_temp_int_enable_check(NRF_TEMP_Type const * p_reg, uint32_t mask) in nrf_temp_int_enable_check() argument
167 return p_reg->INTENSET & mask; in nrf_temp_int_enable_check()
A Dnrf_ccm.h182 uint32_t mask);
191 uint32_t mask);
200 uint32_t mask);
395 uint32_t mask) in nrf_ccm_shorts_enable() argument
397 p_reg->SHORTS |= mask; in nrf_ccm_shorts_enable()
403 p_reg->SHORTS &= ~(mask); in nrf_ccm_shorts_disable()
407 uint32_t mask) in nrf_ccm_shorts_set() argument
409 p_reg->SHORTS = mask; in nrf_ccm_shorts_set()
414 p_reg->INTENSET = mask; in nrf_ccm_int_enable()
419 p_reg->INTENCLR = mask; in nrf_ccm_int_disable()
[all …]
A Dnrf_ecb.h125 NRF_STATIC_INLINE void nrf_ecb_int_enable(NRF_ECB_Type * p_reg, uint32_t mask);
133 NRF_STATIC_INLINE void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask);
143 NRF_STATIC_INLINE uint32_t nrf_ecb_int_enable_check(NRF_ECB_Type const * p_reg, uint32_t mask);
195 NRF_STATIC_INLINE void nrf_ecb_int_enable(NRF_ECB_Type * p_reg, uint32_t mask) in nrf_ecb_int_enable() argument
197 p_reg->INTENSET = mask; in nrf_ecb_int_enable()
200 NRF_STATIC_INLINE void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask) in nrf_ecb_int_disable() argument
202 p_reg->INTENCLR = mask; in nrf_ecb_int_disable()
205 NRF_STATIC_INLINE uint32_t nrf_ecb_int_enable_check(NRF_ECB_Type const * p_reg, uint32_t mask) in nrf_ecb_int_enable_check() argument
207 return p_reg->INTENSET & mask; in nrf_ecb_int_enable_check()
A Dnrf_rtc.h124 NRF_STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_reg, uint32_t mask);
132 NRF_STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_reg, uint32_t mask);
271 NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask);
302 NRF_STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_reg, uint32_t mask) in nrf_rtc_int_enable() argument
304 p_reg->INTENSET = mask; in nrf_rtc_int_enable()
307 NRF_STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_reg, uint32_t mask) in nrf_rtc_int_disable() argument
309 p_reg->INTENCLR = mask; in nrf_rtc_int_disable()
314 return p_reg->INTENSET & mask; in nrf_rtc_int_enable_check()
391 NRF_STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask) in nrf_rtc_event_enable() argument
393 p_reg->EVTENSET = mask; in nrf_rtc_event_enable()
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A Dnrf_kmu.h133 NRF_STATIC_INLINE void nrf_kmu_int_enable(NRF_KMU_Type * p_reg, uint32_t mask);
141 NRF_STATIC_INLINE void nrf_kmu_int_disable(NRF_KMU_Type * p_reg, uint32_t mask);
151 NRF_STATIC_INLINE uint32_t nrf_kmu_int_enable_check(NRF_KMU_Type const * p_reg, uint32_t mask);
225 NRF_STATIC_INLINE void nrf_kmu_int_enable(NRF_KMU_Type * p_reg, uint32_t mask) in nrf_kmu_int_enable() argument
227 p_reg->INTENSET = mask; in nrf_kmu_int_enable()
230 NRF_STATIC_INLINE void nrf_kmu_int_disable(NRF_KMU_Type * p_reg, uint32_t mask) in nrf_kmu_int_disable() argument
232 p_reg->INTENCLR = mask; in nrf_kmu_int_disable()
235 NRF_STATIC_INLINE uint32_t nrf_kmu_int_enable_check(NRF_KMU_Type const * p_reg, uint32_t mask) in nrf_kmu_int_enable_check() argument
237 return p_reg->INTENSET & mask; in nrf_kmu_int_enable_check()
A Dnrf_comp.h282 NRF_STATIC_INLINE void nrf_comp_int_enable(NRF_COMP_Type * p_reg, uint32_t mask);
292 NRF_STATIC_INLINE void nrf_comp_int_disable(NRF_COMP_Type * p_reg, uint32_t mask);
332 NRF_STATIC_INLINE void nrf_comp_shorts_enable(NRF_COMP_Type * p_reg, uint32_t mask);
438 NRF_STATIC_INLINE void nrf_comp_int_enable(NRF_COMP_Type * p_reg, uint32_t mask) in nrf_comp_int_enable() argument
440 p_reg->INTENSET = mask; in nrf_comp_int_enable()
443 NRF_STATIC_INLINE void nrf_comp_int_disable(NRF_COMP_Type * p_reg, uint32_t mask) in nrf_comp_int_disable() argument
445 p_reg->INTENCLR = mask; in nrf_comp_int_disable()
465 NRF_STATIC_INLINE void nrf_comp_shorts_enable(NRF_COMP_Type * p_reg, uint32_t mask) in nrf_comp_shorts_enable() argument
467 p_reg->SHORTS |= mask; in nrf_comp_shorts_enable()
470 NRF_STATIC_INLINE void nrf_comp_shorts_disable(NRF_COMP_Type * p_reg, uint32_t mask) in nrf_comp_shorts_disable() argument
[all …]
A Dnrf_twim.h463 uint32_t mask) in nrf_twim_shorts_enable() argument
465 p_reg->SHORTS |= mask; in nrf_twim_shorts_enable()
469 uint32_t mask) in nrf_twim_shorts_disable() argument
471 p_reg->SHORTS &= ~(mask); in nrf_twim_shorts_disable()
475 uint32_t mask) in nrf_twim_int_enable() argument
477 p_reg->INTENSET = mask; in nrf_twim_int_enable()
481 uint32_t mask) in nrf_twim_int_disable() argument
483 p_reg->INTENCLR = mask; in nrf_twim_int_disable()
488 return p_reg->INTENSET & mask; in nrf_twim_int_enable_check()
588 uint32_t mask) in nrf_twim_shorts_set() argument
[all …]
A Dnrf_pwm.h318 uint32_t mask);
327 uint32_t mask);
336 uint32_t mask);
345 uint32_t mask);
572 p_reg->SHORTS |= mask; in nrf_pwm_shorts_enable()
577 p_reg->SHORTS &= ~(mask); in nrf_pwm_shorts_disable()
582 p_reg->SHORTS = mask; in nrf_pwm_shorts_set()
587 p_reg->INTENSET = mask; in nrf_pwm_int_enable()
592 p_reg->INTENCLR = mask; in nrf_pwm_int_disable()
597 p_reg->INTEN = mask; in nrf_pwm_int_set()
[all …]
/lk-master/external/lib/lwip/core/ipv6/
A Dip6_addr.c39 struct ip_addr *mask) in ip_addr_netcmp() argument
41 return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) && in ip_addr_netcmp()
42 (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) && in ip_addr_netcmp()
43 (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) && in ip_addr_netcmp()
44 (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3])); in ip_addr_netcmp()
/lk-master/lib/fs/ext2/
A Dext2_fs.h315 #define EXT2_HAS_COMPAT_FEATURE(sb,mask) \ argument
316 ( (sb).s_feature_compat & cpu_to_le32(mask) )
317 #define EXT2_HAS_RO_COMPAT_FEATURE(sb,mask) \ argument
318 ( (sb).s_feature_ro_compat & cpu_to_le32(mask) )
320 ( (sb).s_feature_incompat & cpu_to_le32(mask) )
322 (sb).s_feature_compat |= cpu_to_le32(mask)
324 (sb).s_feature_ro_compat |= cpu_to_le32(mask)
326 (sb).s_feature_incompat |= cpu_to_le32(mask)
328 (sb).s_feature_compat &= ~cpu_to_le32(mask)
330 (sb).s_feature_ro_compat &= ~cpu_to_le32(mask)
[all …]
/lk-master/platform/mediatek/common/gic/
A Dmt_gic_v3.c272 unsigned int mask = 1 << (irq % 32); in mt_irq_mask() local
283 unsigned int mask = 1 << (irq % 32); in mt_irq_unmask() local
303 int mt_irq_mask_all(struct mtk_irq_mask *mask) { in mt_irq_mask_all() argument
306 if (mask) { in mt_irq_mask_all()
308 mask->mask[i] = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_ENABLE_SET + i * 4); in mt_irq_mask_all()
314 mask->header = IRQ_MASK_HEADER; in mt_irq_mask_all()
315 mask->footer = IRQ_MASK_FOOTER; in mt_irq_mask_all()
331 if (!mask) { in mt_irq_mask_restore()
334 if (mask->header != IRQ_MASK_HEADER) { in mt_irq_mask_restore()
337 if (mask->footer != IRQ_MASK_FOOTER) { in mt_irq_mask_restore()
[all …]
/lk-master/external/platform/nrfx/drivers/src/
A Dnrfx_ppi.c209 uint32_t mask = NRFX_PPI_ALL_APP_GROUPS_MASK; in nrfx_ppi_free_all() local
215 for (group = NRF_PPI_CHANNEL_GROUP0; mask != 0; mask &= ~group_to_mask(group), group++) in nrfx_ppi_free_all()
217 if (mask & group_to_mask(group)) in nrfx_ppi_free_all()
231 uint32_t mask = 0; in nrfx_ppi_channel_alloc() local
234 mask = NRFX_PPI_PROG_APP_CHANNELS_MASK; in nrfx_ppi_channel_alloc()
236 mask != 0; in nrfx_ppi_channel_alloc()
237 mask &= ~nrfx_ppi_channel_to_mask(channel), channel++) in nrfx_ppi_channel_alloc()
379 uint32_t mask = 0; in nrfx_ppi_group_alloc() local
384 mask = NRFX_PPI_ALL_APP_GROUPS_MASK; in nrfx_ppi_group_alloc()
385 for (group = NRF_PPI_CHANNEL_GROUP0; mask != 0; mask &= ~group_to_mask(group), group++) in nrfx_ppi_group_alloc()
[all …]
A Dnrfx_rtc.c101 uint32_t mask = NRF_RTC_INT_TICK_MASK | in nrfx_rtc_uninit() local
112 nrf_rtc_event_disable(p_instance->p_reg, mask); in nrfx_rtc_uninit()
113 nrf_rtc_int_disable(p_instance->p_reg, mask); in nrfx_rtc_uninit()
226 uint32_t mask = NRF_RTC_INT_TICK_MASK; in nrfx_rtc_tick_enable() local
229 nrf_rtc_event_enable(p_instance->p_reg, mask); in nrfx_rtc_tick_enable()
239 uint32_t mask = NRF_RTC_INT_TICK_MASK; in nrfx_rtc_tick_disable() local
242 nrf_rtc_int_disable(p_instance->p_reg, mask); in nrfx_rtc_tick_disable()
249 uint32_t mask = NRF_RTC_INT_OVERFLOW_MASK; in nrfx_rtc_overflow_enable() local
252 nrf_rtc_event_enable(p_instance->p_reg, mask); in nrfx_rtc_overflow_enable()
261 uint32_t mask = NRF_RTC_INT_OVERFLOW_MASK; in nrfx_rtc_overflow_disable() local
[all …]
/lk-master/external/platform/pico/rp2_common/hardware_base/include/hardware/
A Daddress_mapped.h83 inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { in hw_set_bits() argument
84 *(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask; in hw_set_bits()
93 inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { in hw_clear_bits() argument
94 *(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask; in hw_clear_bits()
103 inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { in hw_xor_bits() argument
104 *(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask; in hw_xor_bits()
/lk-master/top/include/lk/
A Dbits.h38 unsigned long mask = 1UL << BITMAP_BIT_IN_INT(bit); in bitmap_set() local
39 return atomic_or(&((int *)bitmap)[BITMAP_INT(bit)], mask) & mask ? 1 : 0; in bitmap_set()
43 unsigned long mask = 1UL << BITMAP_BIT_IN_INT(bit); in bitmap_clear() local
45 return atomic_and(&((int *)bitmap)[BITMAP_INT(bit)], ~mask) & mask ? 1:0; in bitmap_clear()
/lk-master/arch/arm64/include/arch/
A Dasm_macros.h19 .macro tbzmask, reg, mask, label, shift=0
22 .elseif \mask == 1 << \shift
25 tbzmask \reg, \mask, \label, "(\shift + 1)"
29 .macro tbnzmask, reg, mask, label, shift=0
32 .elseif \mask == 1 << \shift
35 tbnzmask \reg, \mask, \label, "(\shift + 1)"

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