Home
last modified time | relevance | path

Searched refs:pins (Results 1 – 11 of 11) sorted by relevance

/lk-master/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/inc/
A Dpinint_15xx.h103 pPININT->ISEL &= ~pins; in Chip_PININT_SetPinModeEdge()
114 pPININT->ISEL |= pins; in Chip_PININT_SetPinModeLevel()
136 STATIC INLINE void Chip_PININT_EnableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins) in Chip_PININT_EnableIntHigh() argument
138 pPININT->SIENR = pins; in Chip_PININT_EnableIntHigh()
149 pPININT->CIENR = pins; in Chip_PININT_DisableIntHigh()
171 STATIC INLINE void Chip_PININT_EnableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins) in Chip_PININT_EnableIntLow() argument
173 pPININT->SIENF = pins; in Chip_PININT_EnableIntLow()
184 pPININT->CIENF = pins; in Chip_PININT_DisableIntLow()
205 pPININT->RISE = pins; in Chip_PININT_ClearRiseStates()
226 pPININT->FALL = pins; in Chip_PININT_ClearFallStates()
[all …]
A Dgpio_15xx.h361 STATIC INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) in Chip_GPIO_SetPortOutHigh() argument
363 pGPIO->SET[port] = pins; in Chip_GPIO_SetPortOutHigh()
403 STATIC INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) in Chip_GPIO_SetPortOutLow() argument
405 pGPIO->CLR[port] = pins; in Chip_GPIO_SetPortOutLow()
431 STATIC INLINE void Chip_GPIO_SetPortToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins) in Chip_GPIO_SetPortToggle() argument
433 pGPIO->NOT[port] = pins; in Chip_GPIO_SetPortToggle()
/lk-master/external/platform/nrfx/drivers/include/
A Dnrfx_qspi.h53 nrf_qspi_pins_t pins; /**< Pin configuration structure. */ member
84 .pins = { \
/lk-master/external/platform/pico/rp2_common/hardware_pio/
A Dpio.c155 void pio_sm_set_pins(PIO pio, uint sm, uint32_t pins) { in pio_sm_set_pins() argument
164 pio_sm_exec(pio, sm, pio_encode_set(pio_pins, pins & 0x1fu)); in pio_sm_set_pins()
167 pins >>= 5; in pio_sm_set_pins()
/lk-master/external/platform/lpc15xx/lpcopen/periph_gpio/example/
A Dreadme.dox37 * pins at once usnig the GPIO direction setup and masked write oeprations.<br>
/lk-master/external/platform/lpc15xx/lpcopen/periph_clkout/example/
A Dreadme.dox38 * comments in the code for mapped pins for supported boards.<br>
/lk-master/target/stm32746g-eval2/
A Dinit.c45 #error need to configure gpio pins for debug uart in target_early_init()
/lk-master/target/stm32f746g-disco/
A Dinit.c46 #error need to configure gpio pins for debug uart in target_early_init()
/lk-master/external/platform/nrfx/drivers/src/
A Dnrfx_qspi.c128 if (!qspi_pins_configure(&p_config->pins)) in nrfx_qspi_init()
/lk-master/target/dartuinoP0/
A Dinit.c66 #error need to configure gpio pins for debug uart in target_early_init()
/lk-master/external/platform/nrfx/
A DCHANGELOG.md41 …during uninitialization of the drivers. Now every driver restores utilized pins to default setting.

Completed in 12 milliseconds