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Searched refs:GENMASK_32 (Results 1 – 25 of 63) sorted by relevance

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/optee_os-3.20.0/core/include/drivers/
A Dstm32mp13_rcc.h343 #define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4)
347 #define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16)
1744 #define RCC_IDR_ID_MASK GENMASK_32(31, 0)
1748 #define RCC_SIDR_SID_MASK GENMASK_32(31, 0)
1793 #define RCC_SELR_SRC_MASK GENMASK_32(2, 0)
1820 #define RCC_DIVR_DIV_MASK GENMASK_32(5, 0)
1824 #define RCC_APBXDIV_MASK GENMASK_32(2, 0)
1825 #define RCC_MPUDIV_MASK GENMASK_32(2, 0)
1826 #define RCC_AXIDIV_MASK GENMASK_32(2, 0)
1827 #define RCC_MLAHBDIV_MASK GENMASK_32(3, 0)
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A Dstm32mp1_rcc.h238 #define RCC_OFFSET_MASK GENMASK_32(11, 0)
245 #define RCC_SELR_SRC_MASK GENMASK_32(2, 0)
246 #define RCC_SELR_REFCLK_SRC_MASK GENMASK_32(1, 0)
272 #define RCC_DIVR_DIV_MASK GENMASK_32(5, 0)
276 #define RCC_APBXDIV_MASK GENMASK_32(2, 0)
277 #define RCC_MPUDIV_MASK GENMASK_32(2, 0)
278 #define RCC_AXIDIV_MASK GENMASK_32(2, 0)
279 #define RCC_MCUDIV_MASK GENMASK_32(3, 0)
295 #define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4)
300 #define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16)
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A Datmel_shdwc.h26 #define AT91_SHDW_WKUPDBC_MASK GENMASK_32(26, 24)
34 #define AT91_SHDW_WKUPIS_MASK GENMASK_32(31, 16)
39 #define AT91_SHDW_WKUPEN_MASK GENMASK_32(15, 0)
42 #define AT91_SHDW_WKUPT_MASK GENMASK_32(31, 16)
A Dstpmic1.h88 #define LDO_VOLTAGE_MASK GENMASK_32(6, 2)
89 #define BUCK_VOLTAGE_MASK GENMASK_32(7, 2)
96 #define LDO_BUCK_PULL_DOWN_MASK GENMASK_32(1, 0)
137 #define VINLOW_HYST_MASK GENMASK_32(5, 4)
139 #define VINLOW_THRESHOLD_MASK GENMASK_32(3, 1)
142 #define VINLOW_CTRL_REG_MASK GENMASK_32(7, 0)
/optee_os-3.20.0/core/drivers/
A Dstm32_tamp.c53 GENMASK_32(15, 14))
70 GENMASK_32(15, 14))
81 GENMASK_32(15, 14))
84 #define _TAMP_HWCFGR2_TZ GENMASK_32(11, 8)
85 #define _TAMP_HWCFGR2_OR GENMASK_32(7, 0)
88 #define _TAMP_HWCFGR1_BKPREG GENMASK_32(7, 0)
89 #define _TAMP_HWCFGR1_TAMPER GENMASK_32(11, 8)
90 #define _TAMP_HWCFGR1_ACTIVE GENMASK_32(15, 12)
91 #define _TAMP_HWCFGR1_INTERN GENMASK_32(31, 16)
96 #define _TAMP_VERR_MINREV GENMASK_32(3, 0)
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A Ddra7_rng.c49 #define RNG_CONTROL_STARTUP_CYCLES_MASK GENMASK_32(31, 16)
52 #define RNG_CONFIG_MAX_REFIL_CYCLES_MASK GENMASK_32(31, 16)
54 #define RNG_CONFIG_MIN_REFIL_CYCLES_MASK GENMASK_32(7, 0)
57 #define RNG_ALARMCNT_ALARM_TH_MASK GENMASK_32(7, 0)
59 #define RNG_ALARMCNT_SHUTDOWN_TH_MASK GENMASK_32(20, 16)
67 #define RNG_FRO_MASK GENMASK_32(23, 0)
A Datmel_rtc.c33 #define RTC_MR_CORR_MASK GENMASK_32(6, 0)
64 #define RTC_TIME_HOUR_MASK GENMASK_32(5, 0)
66 #define RTC_TIME_MIN_MASK GENMASK_32(6, 0)
68 #define RTC_TIME_SEC_MASK GENMASK_32(6, 0)
72 #define RTC_CAL_DATE_MASK GENMASK_32(5, 0)
74 #define RTC_CAL_DAY_MASK GENMASK_32(2, 0)
76 #define RTC_CAL_MONTH_MASK GENMASK_32(4, 0)
78 #define RTC_CAL_YEAR_MASK GENMASK_32(7, 0)
80 #define RTC_CAL_CENT_MASK GENMASK_32(6, 0)
A Dimx_snvs.c23 #define HPSR_SSM_ST_MASK GENMASK_32(11, 8)
27 #define SNVS_HPSR_SYS_SECURITY_CFG GENMASK_32(14, 12)
29 #define SNVS_HPSR_OTPMK_SYND GENMASK_32(24, 16)
39 #define SNVS_LPMKCR_MKCR_MKS_SEL GENMASK_32(1, 0)
A Dzynqmp_csudma.c29 #define CSUDMA_ADDR_MASK GENMASK_32(31, 2)
31 #define CSUDMA_ADDR_MSB_MASK GENMASK_32(16, 0)
38 #define CSUDMA_IXR_SRC_MASK GENMASK_32(6, 0)
39 #define CSUDMA_IXR_DST_MASK GENMASK_32(7, 1)
A Dstm32_etzpc.c43 #define ETZPC_DECPROT0_MASK GENMASK_32(1, 0)
44 #define ETZPC_HWCFGR_NUM_TZMA_MASK GENMASK_32(7, 0)
46 #define ETZPC_HWCFGR_NUM_PER_SEC_MASK GENMASK_32(15, 8)
48 #define ETZPC_HWCFGR_NUM_AHB_SEC_MASK GENMASK_32(23, 16)
50 #define ETZPC_HWCFGR_CHUNCKS1N4_MASK GENMASK_32(31, 24)
63 #define PERIPH_PM_ATTR_MASK GENMASK_32(2, 0)
65 #define TZMA_PM_VALUE_MASK GENMASK_32(9, 0)
A Dsmccc_trng.c35 #define TRNG_MAJOR_MASK GENMASK_32(30, 16)
37 #define TRNG_MINOR_MASK GENMASK_32(15, 0)
189 (unsigned long)args.a1 & GENMASK_32(16, 0), in smccc_trng_print_info()
191 (unsigned long)args.a2 & GENMASK_32(16, 0), in smccc_trng_print_info()
A Dstm32_gpio.c40 #define GPIO_MODE_MASK GENMASK_32(1, 0)
41 #define GPIO_OSPEED_MASK GENMASK_32(1, 0)
42 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0)
43 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0)
46 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12)
48 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8)
49 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0)
/optee_os-3.20.0/core/arch/arm/plat-imx/registers/
A Dimx6.h128 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK GENMASK_32(10, 5)
131 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK GENMASK_32(4, 4)
134 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK GENMASK_32(20, 20)
136 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK GENMASK_32(26, 21)
139 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK_6UL GENMASK_32(15, 11)
141 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK_6UL GENMASK_32(10, 10)
144 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK_6UL GENMASK_32(26, 26)
146 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK_6UL GENMASK_32(31, 27)
A Dimx7.h65 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_MASK GENMASK_32(13, 11)
68 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_MASK GENMASK_32(10, 10)
71 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_MASK GENMASK_32(26, 26)
72 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_LOCK_OFFSET GENMASK_32(29, 27)
A Dimx6-dcp.h47 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK GENMASK_32(7, 0)
48 #define DCP_STAT_CLEAR GENMASK_32(31, 0)
49 #define DCP_CH_STAT_ERROR_MASK GENMASK_32(23, 0)
/optee_os-3.20.0/core/arch/arm/plat-sam/
A Dsam_sfr.h28 #define AT91_UTMICKTRIM_FREQ GENMASK_32(1, 0)
30 #define AT91_OHCIICR_USB_SUSPEND GENMASK_32(10, 8)
33 #define AT91_SFR_AICREDIR_KEY_MASK GENMASK_32(31, 1)
/optee_os-3.20.0/core/drivers/imx/mu/
A Dimx_mu_8q.c21 #define MU_CR_GIE_MASK GENMASK_32(31, 28)
22 #define MU_CR_RIE_MASK GENMASK_32(27, 24)
23 #define MU_CR_TIE_MASK GENMASK_32(23, 20)
24 #define MU_CR_GIR_MASK GENMASK_32(19, 16)
25 #define MU_CR_F_MASK GENMASK_32(2, 0)
/optee_os-3.20.0/core/arch/arm/plat-k3/drivers/
A Dsa2ul_rng.c42 #define RNG_CONTROL_STARTUP_CYCLES_MASK GENMASK_32(31, 16)
45 #define RNG_CONFIG_MAX_REFIL_CYCLES_MASK GENMASK_32(31, 16)
47 #define RNG_CONFIG_MIN_REFIL_CYCLES_MASK GENMASK_32(7, 0)
50 #define RNG_ALARMCNT_ALARM_TH_MASK GENMASK_32(7, 0)
52 #define RNG_ALARMCNT_SHUTDOWN_TH_MASK GENMASK_32(20, 16)
60 #define RNG_FRO_MASK GENMASK_32(23, 0)
/optee_os-3.20.0/core/drivers/scmi-msg/
A Dvoltage_domain.h29 #define SCMI_VOLTAGE_DOMAIN_COUNT_MASK GENMASK_32(15, 0)
53 #define SCMI_VOLTD_LEVELS_REMAINING_MASK GENMASK_32(31, 16)
61 #define SCMI_VOLTD_LEVELS_COUNT_MASK GENMASK_32(11, 0)
101 #define SCMI_VOLTAGE_DOMAIN_CONFIG_MASK GENMASK_32(3, 0)
A Dclock.h29 #define SCMI_CLOCK_CLOCK_COUNT_MASK GENMASK_32(15, 0)
30 #define SCMI_CLOCK_MAX_PENDING_TRANSITIONS_MASK GENMASK_32(23, 16)
118 #define SCMI_CLOCK_DESCRIBE_RATES_REMAINING_MASK GENMASK_32(31, 16)
124 #define SCMI_CLOCK_DESCRIBE_RATES_COUNT_MASK GENMASK_32(11, 0)
A Dshm_msg.c29 #define MSG_ID_MASK GENMASK_32(7, 0)
32 #define MSG_TYPE_MASK GENMASK_32(9, 8)
35 #define MSG_PROT_ID_MASK GENMASK_32(17, 10)
A Dsmt.c44 #define SMT_MSG_ID_MASK GENMASK_32(7, 0)
47 #define SMT_MSG_TYPE_MASK GENMASK_32(9, 8)
50 #define SMT_MSG_PROT_ID_MASK GENMASK_32(17, 10)
/optee_os-3.20.0/core/arch/arm/plat-stm32mp1/drivers/
A Dstm32mp1_syscfg.c27 #define SYSCFG_CMPCR_RANSRC GENMASK_32(19, 16)
29 #define SYSCFG_CMPCR_RAPSRC GENMASK_32(23, 20)
/optee_os-3.20.0/core/drivers/imx/dcp/include/
A Dlocal.h11 #define DCP_CLK_ENABLE_MASK GENMASK_32(11, 10)
/optee_os-3.20.0/lib/libutee/include/
A Dpta_scmi_client.h82 #define PTA_SCMI_CAPS_MASK GENMASK_32(1, 0)

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