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Searched refs:BIT (Results 1 – 14 of 14) sorted by relevance

/xen-4.10.0-shim-comet/xen/arch/arm/arm64/
A Dinsn.c48 mask = BIT(26) - 1; in aarch64_get_imm_shift_mask()
52 mask = BIT(19) - 1; in aarch64_get_imm_shift_mask()
56 mask = BIT(16) - 1; in aarch64_get_imm_shift_mask()
60 mask = BIT(14) - 1; in aarch64_get_imm_shift_mask()
64 mask = BIT(12) - 1; in aarch64_get_imm_shift_mask()
68 mask = BIT(9) - 1; in aarch64_get_imm_shift_mask()
72 mask = BIT(7) - 1; in aarch64_get_imm_shift_mask()
77 mask = BIT(6) - 1; in aarch64_get_imm_shift_mask()
81 mask = BIT(6) - 1; in aarch64_get_imm_shift_mask()
A Dlivepatch.c211 imm_mask = (BIT(lsb + len) - 1) >> lsb; in reloc_insn_imm()
/xen-4.10.0-shim-comet/xen/include/asm-arm/
A Dgic_v3_its.h41 #define GITS_VALID_BIT BIT(63)
43 #define GITS_CTLR_QUIESCENT BIT(31)
44 #define GITS_CTLR_ENABLE BIT(0)
46 #define GITS_TYPER_PTA BIT(19)
63 #define GITS_BASER_INDIRECT BIT(62)
A Dgic_v3_defs.h147 #define GICR_PENDBASER_PTZ BIT(62)
149 (BIT(63) | GENMASK(61, 59) | GENMASK(55, 52) | \
A Dbitops.h24 #define BIT(nr) (1UL << (nr)) macro
/xen-4.10.0-shim-comet/xen/arch/arm/arm32/
A Dinsn.c61 if ( imm & BIT(23) ) in aarch32_get_branch_offset()
/xen-4.10.0-shim-comet/xen/arch/arm/
A Dgic-v3-its.c366 table_size = ROUNDUP(nr_items * entry_size, BIT(BASER_PAGE_BITS(pagesz))); in its_map_baser()
370 buffer = _xzalloc(table_size, BIT(BASER_PAGE_BITS(pagesz))); in its_map_baser()
486 ret = its_map_baser(basereg, reg, BIT(hw_its->devid_bits)); in gicv3_its_init_single_its()
653 if ( host_devid >= BIT(hw_its->devid_bits) ) in gicv3_its_map_guest_device()
663 nr_events = BIT(fls(nr_events - 1)); in gicv3_its_map_guest_device()
666 if ( nr_events >= BIT(hw_its->evid_bits) ) in gicv3_its_map_guest_device()
A DKconfig1 config 64BIT
10 depends on !64BIT
14 depends on 64BIT
A Dgic-v3-lpi.c394 lpi_data.max_host_lpi_ids = BIT(min(host_lpi_bits, max_lpi_bits)); in gicv3_lpi_init_host_lpis()
401 if ( lpi_data.max_host_lpi_ids > BIT(24) ) in gicv3_lpi_init_host_lpis()
A Dvgic-v3-its.c99 #define DEV_TABLE_ITT_SIZE(x) (BIT(((x) & GENMASK(4, 0)) + 1))
113 if ( reg & BIT(9) ) in get_baser_phys_addr()
127 BUILD_BUG_ON(BIT(sizeof(coll_table_entry_t) * 8) < MAX_VIRT_CPUS); in its_set_collection()
692 BIT(size), valid); in its_handle_mapd()
1359 if ( its->max_devices > BIT(its->devid_bits) ) in vgic_v3_its_mmio_write()
1360 its->max_devices = BIT(its->devid_bits); in vgic_v3_its_mmio_write()
A Dguest_walk.c557 ro_table |= pte.pt.apt & BIT(1); /* Read-Only */ in guest_walk_ld()
A Dvgic.c67 BUILD_BUG_ON(BIT(sizeof(p->lpi_vcpu_id) * 8) < MAX_VIRT_CPUS); in vgic_init_pending_irq()
A Dvgic-v3.c449 unsigned int nr_lpis = BIT((reg & 0x1f) + 1); in vgic_vcpu_enable_lpis()
/xen-4.10.0-shim-comet/docs/man/
A Dxen-tscmode.pod.7253 =head1 TSC INVARIANT BIT and NO_MIGRATE

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