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Searched refs:GICD_CTLR (Results 1 – 5 of 5) sorted by relevance

/xen-4.10.0-shim-comet/xen/include/asm-arm/
A Dgic.h24 #define GICD_CTLR (0x000) macro
/xen-4.10.0-shim-comet/xen/arch/arm/
A Dvgic-v2.c179 case VREG32(GICD_CTLR): in vgic_v2_distr_mmio_read()
423 case VREG32(GICD_CTLR): in vgic_v2_distr_mmio_write()
A Dgic-v3.c268 val = readl_relaxed(base + GICD_CTLR); in gicv3_do_wait_for_rwp()
554 writel_relaxed(0, GICD + GICD_CTLR); in gicv3_dist_init()
592 GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, GICD + GICD_CTLR); in gicv3_dist_init()
A Dgic-v2.c296 writel_gicd(0, GICD_CTLR); in gicv2_dist_init()
328 writel_gicd(GICD_CTL_ENABLE, GICD_CTLR); in gicv2_dist_init()
A Dvgic-v3.c1107 case VREG32(GICD_CTLR): in vgic_v3_distr_mmio_read()
1310 case VREG32(GICD_CTLR): in vgic_v3_distr_mmio_write()

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