Searched refs:GICD_ICFGR (Results 1 – 5 of 5) sorted by relevance
| /xen-4.10.0-shim-comet/xen/arch/arm/ |
| A D | vgic-v2.c | 291 case VRANGE32(GICD_ICFGR, GICD_ICFGRN): in vgic_v2_distr_mmio_read()
296 rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD); in vgic_v2_distr_mmio_read()
299 icfgr = rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)]; in vgic_v2_distr_mmio_read()
545 case VREG32(GICD_ICFGR): /* SGIs */ in vgic_v2_distr_mmio_write()
554 rank = vgic_rank_offset(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD); in vgic_v2_distr_mmio_write()
557 vreg_reg32_update(&rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, in vgic_v2_distr_mmio_write()
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| A D | vgic-v3.c | 737 case VRANGE32(GICD_ICFGR, GICD_ICFGRN): in __vgic_v3_distr_common_mmio_read()
742 rank = vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD); in __vgic_v3_distr_common_mmio_read()
745 icfgr = rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, DABT_WORD)]; in __vgic_v3_distr_common_mmio_read()
852 case VREG32(GICD_ICFGR): /* Restricted to configure SGIs */ in __vgic_v3_distr_common_mmio_write()
855 case VRANGE32(GICD_ICFGR + 4, GICD_ICFGRN): /* PPI + SPIs */ in __vgic_v3_distr_common_mmio_write()
859 rank = vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD); in __vgic_v3_distr_common_mmio_write()
862 vreg_reg32_update(&rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, in __vgic_v3_distr_common_mmio_write()
1199 case VRANGE32(GICD_ICFGR, GICD_ICFGRN): in vgic_v3_distr_mmio_read()
1387 case VRANGE32(GICD_ICFGR, GICD_ICFGRN): in vgic_v3_distr_mmio_write()
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| A D | gic-v2.c | 245 cfg = readl_gicd(GICD_ICFGR + (irq / 16) * 4); in gicv2_set_irq_type()
251 writel_gicd(cfg, GICD_ICFGR + (irq / 16) * 4); in gicv2_set_irq_type()
253 actual = readl_gicd(GICD_ICFGR + (irq / 16) * 4); in gicv2_set_irq_type()
308 writel_gicd(0x0, GICD_ICFGR + (i / 16) * 4); in gicv2_dist_init()
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| A D | gic-v3.c | 499 base = GICD + GICD_ICFGR + (irq / 16) * 4; in gicv3_set_irq_type()
567 writel_relaxed(0, GICD + GICD_ICFGR + (i / 16) * 4); in gicv3_dist_init()
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| /xen-4.10.0-shim-comet/xen/include/asm-arm/ |
| A D | gic.h | 47 #define GICD_ICFGR (0xC00) macro
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