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Searched refs:GICR_ISENABLER0 (Results 1 – 3 of 3) sorted by relevance

/xen-4.10.0-shim-comet/xen/include/asm-arm/
A Dgic_v3_defs.h88 #define GICR_ISENABLER0 (0x0100) macro
/xen-4.10.0-shim-comet/xen/arch/arm/
A Dvgic-v3.c896 case VREG32(GICR_ISENABLER0): in vgic_v3_rdistr_sgi_mmio_read()
973 case VREG32(GICR_ISENABLER0): in vgic_v3_rdistr_sgi_mmio_write()
A Dgic-v3.c793 writel_relaxed(0x0000ffff, GICD_RDIST_SGI_BASE + GICR_ISENABLER0); in gicv3_cpu_init()

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