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Searched refs:MASK_INSR (Results 1 – 13 of 13) sorted by relevance

/xen-4.10.0-shim-comet/xen/arch/x86/hvm/vmx/
A Dvmx.c132 (x2apic_enabled ? dest : MASK_INSR(dest, PI_xAPIC_NDST_MASK))); in vmx_vcpu_block()
153 x2apic_enabled ? dest : MASK_INSR(dest, PI_xAPIC_NDST_MASK)); in vmx_pi_switch_to()
1761 MASK_INSR(type, INTR_INFO_INTR_TYPE_MASK) | in __vmx_inject_exception()
1762 MASK_INSR(trap, INTR_INFO_VECTOR_MASK); in __vmx_inject_exception()
1789 MASK_INSR(trap, INTR_INFO_VECTOR_MASK), in vmx_inject_extint()
1808 MASK_INSR(X86_EVENTTYPE_NMI, INTR_INFO_INTR_TYPE_MASK) | in vmx_inject_nmi()
1809 MASK_INSR(TRAP_nmi, INTR_INFO_VECTOR_MASK), in vmx_inject_nmi()
1891 MASK_INSR(_event.type, INTR_INFO_INTR_TYPE_MASK) | in vmx_inject_event()
1892 MASK_INSR(_event.vector, INTR_INFO_VECTOR_MASK), in vmx_inject_event()
3447 MASK_INSR(X86_EVENTTYPE_NMI, INTR_INFO_INTR_TYPE_MASK)) ) in vmx_idtv_reinject()
[all …]
A Dvvmx.c2267 u32 valid_mask = MASK_INSR(X86_EVENTTYPE_HW_EXCEPTION, in nvmx_n2_vmexit_handler()
/xen-4.10.0-shim-comet/tools/tests/x86_emulator/
A Dx86-emulate.h35 #define MASK_INSR(v, m) (((v) * ((m) & -(m))) & (m)) macro
/xen-4.10.0-shim-comet/xen/include/xen/
A Dlib.h65 #define MASK_INSR(v, m) (((v) * ((m) & -(m))) & (m)) macro
/xen-4.10.0-shim-comet/xen/arch/x86/pv/
A Dgrant_table.c47 pte_flags |= MASK_INSR((grant_flags >> _GNTMAP_guest_avail0), _PAGE_AVAIL); in grant_to_pte_flags()
/xen-4.10.0-shim-comet/xen/arch/x86/hvm/
A Dvmsi.c253 *pval = MASK_INSR(msi_desc->msi_attrib.guest_masked, in msixtbl_read()
256 *pval |= (u64)MASK_INSR(msi_desc->msi_attrib.guest_masked, in msixtbl_read()
/xen-4.10.0-shim-comet/xen/arch/x86/x86_emulate/
A Dx86_emulate.h528 MASK_INSR((ext), X86EMUL_OPC_EXT_MASK))
A Dx86_emulate.c2199 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_twobyte()
2216 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_twobyte()
2228 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_twobyte()
2257 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_twobyte()
2264 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_twobyte()
2304 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_0f38()
2347 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_0f3a()
2479 opcode = b | MASK_INSR(0x0f, X86EMUL_OPC_EXT_MASK); in x86_decode()
2485 opcode = b | MASK_INSR(0x0f38, X86EMUL_OPC_EXT_MASK); in x86_decode()
2490 opcode = b | MASK_INSR(0x0f3a, X86EMUL_OPC_EXT_MASK); in x86_decode()
[all …]
/xen-4.10.0-shim-comet/xen/include/asm-x86/
A Ddomain.h488 #define IOPL(val) MASK_INSR(val, X86_EFLAGS_IOPL)
/xen-4.10.0-shim-comet/tools/libxl/
A Dlibxl_arm.c990 val = MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI, in libxl__arch_domain_init_hw_description()
993 val |= MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL, in libxl__arch_domain_init_hw_description()
A Dlibxl_internal.h138 #define MASK_INSR(v, m) (((v) * ((m) & -(m))) & (m)) macro
/xen-4.10.0-shim-comet/xen/arch/x86/
A Dphysdev.c418 curr->arch.pv_vcpu.iopl = MASK_INSR(set_iopl.iopl, X86_EFLAGS_IOPL); in do_physdev_op()
/xen-4.10.0-shim-comet/xen/arch/arm/
A Ddomain_build.c2048 val = MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI, in evtchn_fixup()
2051 val |= MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL, in evtchn_fixup()

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