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Searched refs:rdmsrl (Results 1 – 25 of 38) sorted by relevance

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/xen-4.10.0-shim-comet/xen/arch/x86/acpi/
A Dsuspend.c33 rdmsrl(MSR_SHADOW_GS_BASE, saved_kernel_gs_base); in save_rest_processor_state()
34 rdmsrl(MSR_CSTAR, saved_cstar); in save_rest_processor_state()
35 rdmsrl(MSR_LSTAR, saved_lstar); in save_rest_processor_state()
39 rdmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp); in save_rest_processor_state()
40 rdmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip); in save_rest_processor_state()
/xen-4.10.0-shim-comet/xen/arch/x86/cpu/mtrr/
A Dgeneric.c32 rdmsrl(MSR_IA32_MTRR_PHYSBASE(index), vr->base); in get_mtrr_var_range()
49 rdmsrl(block->base_msr + i, *p); in get_fixed_ranges()
73 rdmsrl(MSR_MTRRcap, msr_content); in get_mtrr_state()
80 rdmsrl(MSR_MTRRdefType, msr_content); in get_mtrr_state()
85 rdmsrl(MSR_MTRRcap, mtrr_state.mtrr_cap); in get_mtrr_state()
190 rdmsrl(MSR_K8_SYSCFG, syscfg); in print_mtrr_state()
192 rdmsrl(MSR_K8_TOP_MEM2, tom2); in print_mtrr_state()
245 rdmsrl(msr, msr_content); in set_fixed_range()
281 rdmsrl(MSR_IA32_MTRR_PHYSMASK(reg), _mask); in generic_get_mtrr()
420 rdmsrl(MSR_MTRRdefType, deftype); in prepare_set()
[all …]
/xen-4.10.0-shim-comet/xen/arch/x86/oprofile/
A Dop_model_athlon.c36 #define CTR_READ(msr_content,msrs,c) do {rdmsrl(msrs->counters[(c)].addr, (msr_content));} while (0)
262 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl); in handle_ibs()
264 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val); in handle_ibs()
271 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val); in handle_ibs()
282 rdmsrl(MSR_AMD64_IBSOPCTL, ctl); in handle_ibs()
285 rdmsrl(MSR_AMD64_IBSOPRIP, val); in handle_ibs()
291 rdmsrl(MSR_AMD64_IBSOPDATA, val); in handle_ibs()
293 rdmsrl(MSR_AMD64_IBSOPDATA2, val); in handle_ibs()
295 rdmsrl(MSR_AMD64_IBSOPDATA3, val); in handle_ibs()
297 rdmsrl(MSR_AMD64_IBSDCLINAD, val); in handle_ibs()
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A Dop_model_p4.c354 #define ESCR_READ(escr,ev,i) do {rdmsrl(ev->bindings[(i)].escr_address, (escr));} while (0)
365 #define CCCR_READ(msr_content, i) do {rdmsrl(p4_counters[(i)].cccr_address, (msr_content));} while …
370 #define CTR_READ(msr_content,i) do {rdmsrl(p4_counters[(i)].counter_address, (msr_content));} while…
542 rdmsrl(MSR_IA32_MISC_ENABLE, msr_content); in p4_setup_ctrs()
550 rdmsrl(p4_counters[VIRT_CTR(stag, i)].cccr_address, msr_content); in p4_setup_ctrs()
558 rdmsrl(p4_unused_cccr[i], msr_content); in p4_setup_ctrs()
A Dnmi_int.c109 rdmsrl(counters[i].addr, counters[i].value); in nmi_cpu_save_registers()
113 rdmsrl(controls[i].addr, controls[i].value); in nmi_cpu_save_registers()
A Dop_model_ppro.c51 #define CTRL_READ(msr_content,msrs,c) do {rdmsrl((msrs->controls[(c)].addr), (msr_content));} while…
145 rdmsrl(msrs->counters[i].addr, val); in ppro_check_ctrs()
/xen-4.10.0-shim-comet/xen/arch/x86/cpu/
A Dvpmu_intel.c130 rdmsrl(MSR_P6_PERFCTR(i), cnt); in handle_pmc_quirk()
142 rdmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, cnt); in handle_pmc_quirk()
283 rdmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, fixed_counters[i]); in __core2_vpmu_save()
285 rdmsrl(MSR_IA32_PERFCTR0 + i, xen_pmu_cntr_pair[i].counter); in __core2_vpmu_save()
288 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, core2_vpmu_cxt->global_status); in __core2_vpmu_save()
619 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, core2_vpmu_cxt->global_ctrl); in core2_vpmu_do_wrmsr()
740 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, *msr_content); in core2_vpmu_do_rdmsr()
743 rdmsrl(msr, *msr_content); in core2_vpmu_do_rdmsr()
810 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, msr_content); in core2_vpmu_do_interrupt()
883 rdmsrl(MSR_IA32_MISC_ENABLE, msr_content); in vmx_vpmu_initialise()
[all …]
A Dcentaur.c27 rdmsrl(MSR_VIA_FCR, msr_content); in init_c3()
35 rdmsrl(MSR_VIA_RNG, msr_content); in init_c3()
A Damd.c378 rdmsrl(MSR_AMD_OSVW_ID_LENGTH, osvw_len); in cpu_has_amd_erratum()
383 rdmsrl(MSR_AMD_OSVW_STATUS + (osvw_id >> 6), in cpu_has_amd_erratum()
467 rdmsrl(MSR_K8_SYSCFG, syscfg); in check_syscfg_dram_mod_en()
541 rdmsrl(MSR_K7_HWCR, value); in init_amd()
600 rdmsrl(MSR_K8_EXT_FEATURE_MASK, value); in init_amd()
656 rdmsrl(MSR_AMD64_LS_CFG, value); in init_amd()
668 rdmsrl(MSR_AMD64_DE_CFG, value); in init_amd()
698 rdmsrl(MSR_F10_BU_CFG2, value); in init_amd()
A Dmwait-idle.c807 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); in auto_demotion_disable()
822 rdmsrl(MSR_IA32_POWER_CTL, msr_bits); in c1e_promotion_disable()
1011 rdmsrl(MSR_PKGC6_IRTL, msr); in bxt_idle_state_table_update()
1018 rdmsrl(MSR_PKGC7_IRTL, msr); in bxt_idle_state_table_update()
1025 rdmsrl(MSR_PKGC8_IRTL, msr); in bxt_idle_state_table_update()
1032 rdmsrl(MSR_PKGC9_IRTL, msr); in bxt_idle_state_table_update()
1039 rdmsrl(MSR_PKGC10_IRTL, msr); in bxt_idle_state_table_update()
1065 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr); in sklh_idle_state_table_update()
1073 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); in sklh_idle_state_table_update()
A Dvpmu_amd.c285 rdmsrl(counters[i], counter_regs[i]); in context_save()
427 rdmsrl(msr, *msr_content); in amd_vpmu_do_rdmsr()
482 rdmsrl(ctrls[i], ctrl); in amd_vpmu_dump()
483 rdmsrl(counters[i], cntr); in amd_vpmu_dump()
580 rdmsrl(ctrls[i], ctrl_rsvd[i]); in amd_vpmu_init()
/xen-4.10.0-shim-comet/xen/arch/x86/cpu/mcheck/
A Dmce_intel.c71 rdmsrl(MSR_IA32_THERM_STATUS, msr_content); in intel_thermal_interrupt()
124 rdmsrl(MSR_IA32_MISC_ENABLE, msr_content); in intel_init_thermal()
167 rdmsrl(MSR_IA32_THERM_INTERRUPT, msr_content); in intel_init_thermal()
170 rdmsrl(MSR_IA32_MISC_ENABLE, msr_content); in intel_init_thermal()
188 rdmsrl(msr, ext->mc_msr[ext->mc_msrs].value); in intel_get_extended_msr()
498 rdmsrl(msr, val); in do_cmci_discover()
509 rdmsrl(msr, val); in do_cmci_discover()
630 rdmsrl(msr, val); in clear_cmci()
756 rdmsrl(MSR_IA32_MCG_CAP, msr_content); in intel_init_mca()
837 rdmsrl(MSR_IA32_MCx_CTL(i), msr_content); in intel_init_mce()
A Damd_nonfatal.c218 rdmsrl(MSR_IA32_MCx_MISC(4), value); in amd_nonfatal_mcheck_init()
A Dmce.h85 rdmsrl(msr, val); in mca_rdmsr()
/xen-4.10.0-shim-comet/xen/include/asm-x86/
A Dmsr.h19 #define rdmsrl(msr,val) do { unsigned long a__,b__; \ macro
158 rdmsrl(MSR_FS_BASE, base); in rdfsbase()
170 rdmsrl(MSR_GS_BASE, base); in rdgsbase()
A Dapic.h91 rdmsrl(APIC_MSR_BASE + (reg >> 4), msr_content); in apic_rdmsr()
/xen-4.10.0-shim-comet/xen/arch/x86/x86_64/
A Dmmconf-fam10h.c69 rdmsrl(address, val); in get_fam10h_pci_mmconf_base()
77 rdmsrl(address, val); in get_fam10h_pci_mmconf_base()
148 rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, val); in fam10h_check_enable_mmcfg()
A Dtraps.c52 rdmsrl(MSR_SHADOW_GS_BASE, crs[7]); in read_registers()
155 rdmsrl(this_cpu(ler_msr), from); in show_registers()
156 rdmsrl(this_cpu(ler_msr) + 1, to); in show_registers()
/xen-4.10.0-shim-comet/xen/arch/x86/
A Dnmi.c346 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); in setup_p4_watchdog()
515 rdmsrl(MSR_P4_IQ_CCCR0, msr_content); in nmi_watchdog_tick()
531 rdmsrl(MSR_P6_PERFCTR(0), msr_content); in nmi_watchdog_tick()
543 rdmsrl(MSR_K7_PERFCTR0, msr_content); in nmi_watchdog_tick()
A Dmicrocode_intel.c113 rdmsrl(MSR_IA32_PLATFORM_ID, msr_content); in collect_cpu_info()
122 rdmsrl(MSR_IA32_UCODE_REV, msr_content); in collect_cpu_info()
305 rdmsrl(MSR_IA32_UCODE_REV, msr_content); in apply_microcode()
A Dapic.c305 rdmsrl(MSR_IA32_APICBASE, msr_content); in disable_local_APIC()
313 rdmsrl(MSR_IA32_APICBASE, msr_content); in disable_local_APIC()
481 rdmsrl(MSR_IA32_APICBASE, msr_content); in __enable_x2apic()
746 rdmsrl(MSR_IA32_APICBASE, msr_content); in lapic_resume()
1455 rdmsrl(MSR_IA32_APICBASE, msr_contents); in current_local_apic_mode()
A De820.c462 rdmsrl(MSR_MTRRcap, mtrr_cap); in mtrr_top_of_ram()
463 rdmsrl(MSR_MTRRdefType, mtrr_def); in mtrr_top_of_ram()
479 rdmsrl(MSR_IA32_MTRR_PHYSBASE(i), base); in mtrr_top_of_ram()
480 rdmsrl(MSR_IA32_MTRR_PHYSMASK(i), mask); in mtrr_top_of_ram()
/xen-4.10.0-shim-comet/xen/arch/x86/acpi/cpufreq/
A Dcpufreq.c142 rdmsrl(cmd->addr.msr.reg, cmd->val); in do_drv_read()
162 rdmsrl(cmd->addr.msr.reg, msr_content); in do_drv_write()
253 rdmsrl(MSR_IA32_APERF, readin->aperf.whole); in read_measured_perf_ctrs()
254 rdmsrl(MSR_IA32_MPERF, readin->mperf.whole); in read_measured_perf_ctrs()
A Dpowernow.c69 rdmsrl(MSR_K8_HWCR, msr_content); in update_cpb()
185 rdmsrl(MSR_PSTATE_CUR_LIMIT, msr_content); in get_cpu_data()
/xen-4.10.0-shim-comet/xen/arch/x86/hvm/vmx/
A Dvmcs.c242 rdmsrl(MSR_IA32_VMX_MISC, _vmx_misc_cap); in vmx_init_vmcs_config()
271 rdmsrl(MSR_IA32_VMX_EPT_VPID_CAP, _vmx_ept_vpid_cap); in vmx_init_vmcs_config()
370 rdmsrl(MSR_IA32_VMX_VMFUNC, _vmx_vmfunc); in vmx_init_vmcs_config()
624 rdmsrl(MSR_IA32_VMX_CR0_FIXED0, vmx_cr0_fixed0); in _vmx_cpu_up()
625 rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx_cr0_fixed1); in _vmx_cpu_up()
1158 rdmsrl(MSR_IA32_SYSENTER_CS, sysenter_cs); in construct_vmcs()
1160 rdmsrl(MSR_IA32_SYSENTER_EIP, sysenter_eip); in construct_vmcs()
1258 rdmsrl(MSR_IA32_CR_PAT, host_pat); in construct_vmcs()
1402 rdmsrl(msr, msr_area_elem->data); in vmx_add_msr()

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