1 /* 2 * Copyright (C) 2017-2019 Alibaba Group Holding Limited 3 */ 4 /****************************************************************************** 5 * @file drv_dpu.h 6 * @brief header file for dpu driver 7 * @version V1.6 8 * @date 27. May 2019 9 * @model dpu 10 ******************************************************************************/ 11 12 #ifndef _DRV_DPU_H_ 13 #define _DRV_DPU_H_ 14 15 #include <stdint.h> 16 #include <drv/common.h> 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 /// definition for dpu handle. 23 typedef void *dpu_handle_t; 24 typedef uint32_t dpu_rgba32_t; /* rrggbbaa */ 25 26 /*----- DPU interrupt event type -----*/ 27 typedef enum { 28 DPU_EVENT_VSYNC = 0, ///< VSYNC event 29 DPU_EVENT_HSYNC, ///< HSYNC event 30 } dpu_event_e; 31 32 /*----- DPU extend error type -----*/ 33 typedef enum { 34 DPU_ERROR_GET_CONFIG_TYPE = (DRV_ERROR_SPECIFIC + 1), 35 DPU_ERROR_SET_CONFIG_TYPE, 36 } dpu_errno_e; 37 38 /*----- DPU color mode type -----*/ 39 typedef enum { 40 DPU_COLORMODE_RGBA8888 = 0, ///< 32-bit RGBA mode 41 DPU_COLORMODE_ABGR8888, ///< 32-bit ABGR mode 42 DPU_COLORMODE_ARGB8888, ///< 32-bit ARGB mode 43 DPU_COLORMODE_BGRA8888, ///< 32-bit BGRA mode 44 45 DPU_COLORMODE_RGB888, ///< 24-bit RGB mode 46 47 DPU_COLORMODE_RGB565, ///< 16-bit RGB mode 48 DPU_COLORMODE_RGBA5551, ///< 16-bit RGBA mode 49 DPU_COLORMODE_RGBA4444, ///< 16-bit RGBA mode 50 51 DPU_COLORMODE_RGBA3320, ///< 8-bit RGBA mode 52 53 DPU_COLORMODE_L1, ///< 1-bit Grayscale mode from 0(black) to 1 (white) 54 DPU_COLORMODE_L4, ///< 4-bit Grayscale mode from 0(black) to 15 (white) 55 DPU_COLORMODE_L8, ///< 8-bit Grayscale mode from 0(black) to 255 (white) 56 DPU_COLORMODE_PALETTE8, ///< 8-bit Palatte(looked-up table) mode 57 58 DPU_COLORMODE_YUYV, ///< 32-bit/2-pixels YUV422 mode. (Y0 U0 Y1 V0) 59 DPU_COLORMODE_YUY2, ///< 32-bit/2-pixels YUV422 mode. (Y0 U0 Y1 V0) 60 DPU_COLORMODE_YUV420SP, ///< 48-bit/4-pixels YUV420 planar mode. (YYYY..UV..) 61 DPU_COLORMODE_YUV420P, ///< 48-bit/4-pixels YUV420 planar mode. (YYYY..U..V..) 62 } dpu_colormode_e; 63 64 /*----- DPU blend mode type -----*/ 65 typedef enum { 66 /* Blended Color = Cs * Fs + Cd * Fd 67 * Cs: Color of source (previous layer) 68 * Cd: Color of destinaion (current layer) 69 * Fs: Factor of source (previous layer) 70 * Fd: Factor of destinaion (current layer) 71 * 72 * The factors are defined in below blend modes: 73 * Sa = Source alpha (pixel alpha in previous layer) 74 * Da = Destinaion alpha (pixel alpha in current layer) 75 * Ga = Global alpha (global alpha in layer configuration) 76 */ 77 DPU_BLENDMODE_SIMPLE = 0, ///< Sa * Sa + Da * (1 - Sa) 78 DPU_BLENDMODE_CLEAR, ///< 0 79 DPU_BLENDMODE_SRC, ///< Sa 80 DPU_BLENDMODE_SRC_OVER, ///< Sa + Da * (1 - Sa) 81 DPU_BLENDMODE_DST_OVER, ///< Sa * (1 - Da) + Da 82 DPU_BLENDMODE_SRC_IN, ///< Sa * Da 83 DPU_BLENDMODE_DST_IN, ///< Da * Sa 84 DPU_BLENDMODE_SRC_OUT, ///< Sa * (1 - Da) 85 DPU_BLENDMODE_DST_OUT, ///< Da * (1 - Sa) 86 DPU_BLENDMODE_SRC_ATOP, ///< Sa * Da + Da * (1 - Sa) 87 DPU_BLENDMODE_DST_ATOP, ///< Sa * (1 - Da) + Da * Sa 88 DPU_BLENDMODE_ADD, ///< Sa + Da 89 DPU_BLENDMODE_XOR, ///< Sa * (1 - Da) + Da * (1 - Sa) 90 DPU_BLENDMODE_MIX, ///< Sa * Ga + Da 91 } dpu_blendmode_e; 92 93 /*----- LCD signal active mode -----*/ 94 typedef enum { 95 DPU_SIGNAL_ACTIVE_LOW = 0, 96 DPU_SIGNAL_ACTIVE_HIGH = 1, 97 } dpu_signal_polarity_e; 98 99 /** 100 \brief LCD display timing info 101 */ 102 typedef struct { 103 uint32_t resolution_x; ///< Horizontal valid data width 104 uint32_t resolution_y; ///< Vertical valid data width 105 uint32_t hsync_width; ///< HSync pulse width 106 uint32_t vsync_width; ///< VSync pluse width 107 uint32_t front_porch_x; ///< HSync front porch 108 uint32_t front_porch_y; ///< VSync front porch 109 uint32_t back_porch_x; ///< HSync back porch 110 uint32_t back_porch_y; ///< VSync back porch 111 } dpu_cfg_display_timing_t; 112 113 /** 114 \brief LCD signal polarity config info 115 */ 116 typedef struct { 117 dpu_signal_polarity_e vsync; ///< vsync signal polarity 118 dpu_signal_polarity_e hsync; ///< hsync signal polarity 119 dpu_signal_polarity_e deta_enable; ///< deta_enable signal polarity 120 dpu_signal_polarity_e pixel_clock; ///< pixel_clock signal polarity 121 } dpu_cfg_display_signal_polarity_t; 122 123 /** 124 \brief DPU layer config info 125 */ 126 typedef struct { 127 void *baseaddr; ///< picture store address 128 dpu_colormode_e colormode; ///< color mode of the picture 129 dpu_blendmode_e blendmode; ///< blend mode with other layer(s) 130 uint32_t resx; ///< resolution width of target display device 131 uint32_t resy; ///< resolution height of target display device 132 int32_t startx; ///< display horizontal position on target device 133 int32_t starty; ///< display vertical position on target device 134 uint32_t sizex; ///< display width on target device 135 uint32_t sizey; ///< display height on target device 136 uint8_t alpha; ///< display diaphaneity 137 } dpu_layer_cfg_t; 138 139 /** 140 \brief DPU cursor info 141 */ 142 typedef struct { 143 uint8_t width; 144 uint8_t height; 145 uint8_t *img_data; 146 } dpu_cursor_info_t; 147 148 ///< Pointer to \ref dpu_event_cb_t : DPU Event call back. 149 typedef void (*dpu_event_cb_t)(dpu_handle_t handle, dpu_event_e event, void *user_data); 150 151 /** 152 \brief Initialize DPU Interface. 153 Initialize the resources needed for the DPU interface 154 \param[in] idx dpu index 155 \param[in] cb_event event call back function \ref dpu_event_cb_t 156 \return pointer to dpu instance 157 */ 158 dpu_handle_t csi_dpu_initialize(int32_t idx, dpu_event_cb_t cb_event, void *user_data); 159 160 /** 161 \brief De-initialize DPU Interface. 162 Stop operation and release the resources used by the interface 163 \param[in] handle dpu handle to operate. 164 \return error code 165 */ 166 int32_t csi_dpu_uninitialize(dpu_handle_t handle); 167 168 /** 169 \brief Start DPU Interface. 170 \param[in] handle dpu handle to operate. 171 \return error code 172 */ 173 int32_t csi_dpu_start(dpu_handle_t handle); 174 175 /** 176 \brief Stop DPU Interface. 177 \param[in] handle dpu handle to operate. 178 \return error code 179 */ 180 int32_t csi_dpu_stop(dpu_handle_t handle); 181 182 /** 183 \brief Configurate display parameters. 184 \param[in] handle dpu handle to operate. 185 \param[in] timing the display's timing parameters. 186 \param[in] polarity the display's signal parameters. 187 \return error code 188 */ 189 int32_t csi_dpu_config_display(dpu_handle_t handle, 190 dpu_cfg_display_timing_t *timing, 191 dpu_cfg_display_signal_polarity_t *polarity); 192 193 /** 194 \brief Wait for display vsync. 195 \param[in] handle dpu handle to operate. 196 \return error code 197 */ 198 int32_t csi_dpu_wait_vsync(dpu_handle_t handle); 199 200 /** 201 \brief Set background color. 202 \param[in] handle dpu handle to operate. 203 \param[in] color the background color. 204 \return error code 205 */ 206 int32_t csi_dpu_set_bgcolor(dpu_handle_t handle, dpu_rgba32_t color); 207 208 /** 209 \brief Set cursor image. 210 \param[in] handle dpu handle to operate. 211 \param[in] img cursor image address. 212 \return error code 213 */ 214 int32_t csi_dpu_cursor_set_img(dpu_handle_t handle, dpu_cursor_info_t *cursor); 215 216 /** 217 \brief Set cursor color palette. 218 \param[in] handle dpu handle to operate. 219 \param[in] index palette index. 220 \param[in] color palette color of index. 221 \return error code 222 */ 223 int32_t csi_dpu_cursor_set_palette(dpu_handle_t handle, uint32_t index, dpu_rgba32_t color); 224 225 /** 226 \brief Enable/Disable cursor 227 \param[in] handle dpu handle to operate. 228 \param[in] enable set cursor enable or not. 0:disable; 1:enable. 229 \return error code 230 */ 231 int32_t csi_dpu_cursor_enable(dpu_handle_t handle, int32_t enable); 232 233 /** 234 \brief Set cursor position. 235 \param[in] handle dpu handle to operate. 236 \param[in] x cursor's x position. 237 \param[in] y cursor's y position. 238 \return error code 239 */ 240 int32_t csi_dpu_cursor_set_position(dpu_handle_t handle, uint32_t x, uint32_t y); 241 242 /** 243 \brief Set layer's configuration parameters. 244 \param[in] handle dpu handle to operate. 245 \param[in] layer_id layer index number. 246 \param[in] config layer configuration parameters. 247 \return error code 248 */ 249 int32_t csi_dpu_layer_set_config(dpu_handle_t handle, uint8_t layer_id, dpu_layer_cfg_t *config); 250 251 /** 252 \brief Get layer's configuration parameters. 253 \param[in] handle dpu handle to operate. 254 \param[in] layer_id layer index number. 255 \param[out] config layer configuration parameters. 256 \return error code 257 */ 258 int32_t csi_dpu_layer_get_config(dpu_handle_t handle, uint8_t layer_id, dpu_layer_cfg_t *config); 259 260 /** 261 \brief Enable/Disable layer 262 \param[in] handle dpu handle to operate. 263 \param[in] layer_id layer index number. 264 \param[in] enable Set layer enable or not. 0:disable; 1:enable. 265 \return error code 266 */ 267 int32_t csi_dpu_layer_enable(dpu_handle_t handle, uint8_t layer_id, int32_t enable); 268 269 /** 270 \brief Set layer's palette lookup table color 271 \param[in] handle dpu handle to operate. 272 \param[in] layer_id layer index number. 273 \param[in] index the index of palette. 274 \param[in] color the color of the specific palette index. 275 \return error code 276 */ 277 int32_t csi_dpu_set_palette(dpu_handle_t handle, uint8_t layer_id, 278 uint32_t index, dpu_rgba32_t color); 279 280 #ifdef __cplusplus 281 } 282 #endif 283 284 #endif /* _DRV_DPU_H_ */ 285