1 /*
2  * Copyright (C) 2015-2017 Alibaba Group Holding Limited
3  */
4 
5 #ifndef MPU_H
6 #define MPU_H
7 
8 
9 typedef struct {
10     // MPU type register
11     unsigned int type;
12     // MPU control register
13     unsigned int ctrl;
14     // MPU range number register
15     unsigned int rnr;
16     // MPU region base address register
17     unsigned int rbar;
18     // MPU region attribute and size register
19     unsigned int rasr;
20     // MPU alias registers
21     unsigned int rbar_a1;
22     unsigned int rasr_a1;
23     unsigned int rbar_a2;
24     unsigned int rasr_a2;
25     unsigned int rbar_a3;
26     unsigned int rasr_a3;
27 } MPU_t;
28 
29 
30 /* System Handler Control and State register */
31 #define SHCSR_M                  ((unsigned int*)0xE000ED24UL)
32 
33 /* MPU registers */
34 
35 #define MPU_BASE                 (0xE000ED90UL)
36 #define MPU                      ((MPU_t*)(MPU_BASE))
37 
38 #define MPU_TYPE_IREGION_OFFSET     (16U)
39 
40 #define MPU_TYPE_IREGION_MASK       (0xFFUL << MPU_TYPE_IREGION_OFFSET)
41 
42 #define MPU_TYPE_DREGION_OFFSET     (8U)
43 
44 #define MPU_TYPE_DREGION_MASK       (0xFFUL << MPU_TYPE_DREGION_OFFSET)
45 
46 #define MPU_TYPE_SEPARATE_OFFSET    (0U)
47 
48 #define MPU_TYPE_SEPARATE_MASK      (1UL)
49 
50 #define MPU_CTRL_PRIVDEFENA_OFFSET  (2U)
51 
52 #define MPU_CTRL_PRIVDEFENA_MASK    (1UL << MPU_CTRL_PRIVDEFENA_OFFSET)
53 
54 #define MPU_CTRL_HFNMIENA_OFFSET    (1U)
55 
56 #define MPU_CTRL_HFNMIENA_MASK      (1UL << MPU_CTRL_HFNMIENA_OFFSET)
57 
58 #define MPU_CTRL_ENABLE_OFFSET      (0U)
59 
60 #define MPU_CTRL_ENABLE_MASK        (1UL)
61 
62 #define MPU_RNR_REGION_OFFSET       (0U)
63 
64 #define MPU_RNR_REGION_MASK         (0xFFUL)
65 
66 #define MPU_RBAR_ADDR_OFFSET        (5U)
67 
68 #define MPU_RBAR_ADDR_MASK          (0x7FFFFFFUL << MPU_RBAR_ADDR_OFFSET)
69 
70 #define MPU_RBAR_VALID_OFFSET       (4U)
71 
72 #define MPU_RBAR_VALID_MASK         (1UL << MPU_RBAR_VALID_OFFSET)
73 
74 #define MPU_RBAR_REGION_OFFSET      (0U)
75 
76 #define MPU_RBAR_REGION_MASK        (0xFUL)
77 
78 #define MPU_RASR_ATTRS_OFFSET       (16U)
79 
80 #define MPU_RASR_ATTRS_MASK         (0xFFFFUL << MPU_RASR_ATTRS_OFFSET)
81 
82 #define MPU_RASR_XN_OFFSET          (28U)
83 
84 #define MPU_RASR_XN_MASK            (1UL << MPU_RASR_XN_OFFSET)
85 
86 #define MPU_RASR_AP_OFFSET          (24U)
87 
88 #define MPU_RASR_AP_MASK            (0x7UL << MPU_RASR_AP_OFFSET)
89 
90 #define MPU_RASR_TEX_OFFSET         (19U)
91 
92 #define MPU_RASR_TEX_MASK           (0x7UL << MPU_RASR_TEX_OFFSET)
93 
94 #define MPU_RASR_S_OFFSET           (18U)
95 
96 #define MPU_RASR_S_MASK             (1UL << MPU_RASR_S_OFFSET)
97 
98 #define MPU_RASR_C_OFFSET           (17U)
99 
100 #define MPU_RASR_C_MASK             (1UL << MPU_RASR_C_OFFSET)
101 
102 #define MPU_RASR_B_OFFSET           (16U)
103 
104 #define MPU_RASR_B_MASK             (1UL << MPU_RASR_B_OFFSET)
105 
106 #define MPU_RASR_SRD_OFFSET         (8U)
107 
108 #define MPU_RASR_SRD_MASK           (0xFFUL << MPU_RASR_SRD_OFFSET)
109 
110 #define MPU_RASR_SIZE_OFFSET        (1U)
111 
112 #define MPU_RASR_SIZE_MASK          (0x1FUL << MPU_RASR_SIZE_OFFSET)
113 
114 #define MPU_RASR_ENABLE_OFFSET      (0U)
115 
116 #define MPU_RASR_ENABLE_MASK        (1UL)
117 
118 
119 /* MPU regions size */
120 
121 #define MPU_REGION_SIZE_32B      (0x04U)
122 #define MPU_REGION_SIZE_64B      (0x05U)
123 #define MPU_REGION_SIZE_128B     (0x06U)
124 #define MPU_REGION_SIZE_256B     (0x07U)
125 #define MPU_REGION_SIZE_512B     (0x08U)
126 #define MPU_REGION_SIZE_1KB      (0x09U)
127 #define MPU_REGION_SIZE_2KB      (0x0AU)
128 #define MPU_REGION_SIZE_4KB      (0x0BU)
129 #define MPU_REGION_SIZE_8KB      (0x0CU)
130 #define MPU_REGION_SIZE_16KB     (0x0DU)
131 #define MPU_REGION_SIZE_32KB     (0x0EU)
132 #define MPU_REGION_SIZE_64KB     (0x0FU)
133 #define MPU_REGION_SIZE_128KB    (0x10U)
134 #define MPU_REGION_SIZE_256KB    (0x11U)
135 #define MPU_REGION_SIZE_512KB    (0x12U)
136 #define MPU_REGION_SIZE_1MB      (0x13U)
137 #define MPU_REGION_SIZE_2MB      (0x14U)
138 #define MPU_REGION_SIZE_4MB      (0x15U)
139 #define MPU_REGION_SIZE_8MB      (0x16U)
140 #define MPU_REGION_SIZE_16MB     (0x17U)
141 #define MPU_REGION_SIZE_32MB     (0x18U)
142 #define MPU_REGION_SIZE_64MB     (0x19U)
143 #define MPU_REGION_SIZE_128MB    (0x1AU)
144 #define MPU_REGION_SIZE_256MB    (0x1BU)
145 #define MPU_REGION_SIZE_512MB    (0x1CU)
146 #define MPU_REGION_SIZE_1GB      (0x1DU)
147 #define MPU_REGION_SIZE_2GB      (0x1EU)
148 #define MPU_REGION_SIZE_4GB      (0x1FU)
149 
150 #define MPU_AP_NA_NA             (0x00U)
151 #define MPU_AP_RW_NA             (0x01U)
152 #define MPU_AP_RW_RO             (0x02U)
153 #define MPU_AP_RW_RW             (0x03U)
154 #define MPU_AP_RESV              (0x04U)
155 #define MPU_AP_RO_NA             (0x05U)
156 #define MPU_AP_RO_RO             (0x06U)
157 
158 
159 typedef struct {
160     unsigned long base_addr;
161     unsigned char range_no;
162     unsigned char size;
163     unsigned char ext_type;
164     unsigned char access_permission;
165     unsigned char disable_exec;
166     unsigned char subregion_disable;
167     unsigned char shareable;
168     unsigned char cacheable;
169     unsigned char bufferable;
170     unsigned char enable;
171 } MPU_Region_Init_t;
172 
173 #if AOS_COMP_DEBUG
174 /**
175  * set mpu region for memory unauthorized access check
176  *
177  * @param[in]  addr_start   monitor start addr
178  * @param[in]  addr_size    monitor size
179  * @param[in]  mode         prohibit access(0) or read only(>0)
180  */
181 void debug_memory_access_err_check(unsigned long addr_start, unsigned long addr_size, unsigned int mode);
182 void debug_task_stack_ovf_check(char *task_name);
183 void debug_check_mem_access_disable(void);
184 #endif
185 
186 #endif // MPU_H
187 
188