1#include "k_config.h"
2
3@******************************************************************************
4@                                 EQUATES
5@******************************************************************************
6.equ PANIC_CONTEXT_SIZE, 96   @bigger than sizeof(PANIC_CONTEXT)
7
8@******************************************************************************
9@                        CODE GENERATION DIRECTIVES
10@******************************************************************************
11.text
12.align 2
13.thumb
14.syntax unified
15
16#if AOS_COMP_DEBUG
17@******************************************************************************
18@                            EXTERN PARAMETERS
19@******************************************************************************
20.extern panicHandler
21.extern g_crash_steps
22.extern g_panic_contex
23.extern _first_task_restore
24.extern panicRestoreCheck
25
26@******************************************************************************
27@                            EXPORT FUNCTIONS
28@******************************************************************************
29.global	HardFault_Handler
30.global	MemManage_Handler
31.global	BusFault_Handler
32.global	UsageFault_Handler
33
34@******************************************************************************
35@                             FAULT FUNCTIONS
36@******************************************************************************
37.thumb_func
38HardFault_Handler:
39.thumb_func
40MemManage_Handler:
41.thumb_func
42BusFault_Handler:
43.thumb_func
44UsageFault_Handler:
45    PUSH    {R1, LR}
46    BL      panicRestoreCheck
47    POP     {R1, LR}
48    CBZ     R0, unrecoverable_crash
49    BL     _first_task_restore
50
51unrecoverable_crash:
52    @check double crash
53    LDR     R1, =g_crash_steps
54    LDR     R2, [R1]
55    ADD     R3, R2, #1
56    STR     R3, [R1]
57    CBZ     R2, first_panic
58    @return from exc to handle panic
59    MRS     R1, PSP
60    AND     R2, LR, #4          @EXC_RETURN:bit2, 0 MSP, 1 PSP
61    CBNZ    R2, double_panic
62    MRS     R1, MSP
63double_panic:
64    LDR     R0, =double_panic_entry
65    STR     R0, [R1, #24]
66    LDR     R0, [R1, #28]
67    ORR     R0, R0, #0x1000000
68    STR     R0, [R1, #28]       @set thumb mode
69    BX      LR
70
71double_panic_entry:
72    MOV     R0, #0              @double crash, do not save context
73    BL      panicHandler
74    B       .
75
76first_panic:
77    @R0 as PANIC_CONTEXT
78#if DEBUG_PANIC_CONTEXT_IN_STACK > 0
79    LDR     R0, =g_panic_contex
80#else
81    SUB     R0, SP, #PANIC_CONTEXT_SIZE
82    MOV     SP, R0
83#endif
84
85    @R1 as CONTEXT saved by hardware
86    MRS     R1, PSP
87    AND     R2, LR, #4          @EXC_RETURN:bit2, 0 MSP, 1 PSP
88    CBNZ    R2, context_save
89    MRS     R1, MSP
90
91context_save:
92    ADD     R2, R0, #16
93    STM     R2!,{R4-R11}        @ctx save, R4~R11
94
95    LDM     R1, {R4-R11}
96    STM     R0, {R4-R7}         @ctx save, R0~R3
97
98    STM     R2!,{R8-R11}        @ctx save, R12 LR PC xPSR
99
100    @xPSR[9] and EXC_RETURN[4] to determine whether
101    @the previous top-of-stack was at offset 0x20, 0x24, 0x68, or0x6C
102    ADD     R4, R1, #0x20
103#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
104    AND     R3, LR, #0x10       @EXC_RETURN:bit4, 0 floating, 1 non-floating
105    CBNZ    R3, check_aligner
106    ADD     R4, R4, #0x48
107check_aligner:
108#endif
109    LDR     R3, [R1, #28]
110    AND     R3, R3, #0x200      @xPSR:bit9, 0 no-aligner, 1 aligner
111    CBZ     R3, sp_save
112    ADD     R4, R4, #0x4
113sp_save:
114    STM     R2!,{R4}            @ctx save, SP
115
116    MRS     R4, MSP
117    STM     R2!,{R4}            @ctx save, MSP
118
119    MRS     R4, PSP
120    STM     R2!,{R4}            @ctx save, PSP
121
122    MOV     R4, LR
123    STM     R2!,{R4}            @ctx save, EXC_RETURN
124
125    MRS     R4, IPSR
126    STM     R2!,{R4}            @ctx save, EXC_NUMBER
127
128    MRS     R4, PRIMASK
129    STM     R2!,{R4}            @ctx save, PRIMASK
130
131    MRS     R4, FAULTMASK
132    STM     R2!,{R4}            @ctx save, FAULTMASK
133
134    MRS     R4, BASEPRI
135    STM     R2!,{R4}            @ctx save, BASEPRI
136
137    @return from exc to handle panic
138    STR     R0, [R1, #0]
139    LDR     R0, =panic_entry
140    STR     R0, [R1, #24]
141    LDR     R0, [R1, #28]       @set thumb mode
142    ORR     R0, R0, #0x1000000
143    STR     R0, [R1, #28]
144    BX      LR
145
146panic_entry:
147    @set sp to msp
148    MRS     R1, CONTROL
149    BIC     R1, #2
150    MSR     CONTROL, R1
151    ISB
152    BL      panicHandler
153    B       .
154
155#endif
156
157.end
158
159