1/* File: startup_ARMCM3.S 2 * Purpose: startup file for Cortex-M3 devices. Should use with 3 * GCC for ARM Embedded Processors 4 * Version: V2.0 5 * Date: 16 August 2013 6 * 7/* Copyright (c) 2011 - 2013 ARM LIMITED 8 9 All rights reserved. 10 Redistribution and use in source and binary forms, with or without 11 modification, are permitted provided that the following conditions are met: 12 - Redistributions of source code must retain the above copyright 13 notice, this list of conditions and the following disclaimer. 14 - Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 - Neither the name of ARM nor the names of its contributors may be used 18 to endorse or promote products derived from this software without 19 specific prior written permission. 20 * 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 ---------------------------------------------------------------------------*/ 33 .syntax unified 34 .arch armv7-m 35 36 .section .stack 37 .align 3 38#ifdef __STACK_SIZE 39 .equ Stack_Size, __STACK_SIZE 40#else 41 .equ Stack_Size, 0xc00 42#endif 43 .globl __StackTop 44 .globl __StackLimit 45__StackLimit: 46 .space Stack_Size 47 .size __StackLimit, . - __StackLimit 48__StackTop: 49 .size __StackTop, . - __StackTop 50 51 .section .heap 52 .align 3 53#ifdef __HEAP_SIZE 54 .equ Heap_Size, __HEAP_SIZE 55#else 56 .equ Heap_Size, 0x1B000 57#endif 58 .globl __HeapBase 59 .globl __HeapLimit 60__HeapBase: 61 .if Heap_Size 62 .space Heap_Size 63 .endif 64 .size __HeapBase, . - __HeapBase 65__HeapLimit: 66 .size __HeapLimit, . - __HeapLimit 67 68 .section .isr_vector 69 .align 2 70 .globl __isr_vector 71__isr_vector: 72 .word __StackTop /* Top of Stack */ 73 .word Reset_Handler /* Reset Handler */ 74 .word NMI_Handler /* NMI Handler */ 75 .word HardFault_Handler /* Hard Fault Handler */ 76 .word MemManage_Handler /* MPU Fault Handler */ 77 .word BusFault_Handler /* Bus Fault Handler */ 78 .word UsageFault_Handler /* Usage Fault Handler */ 79 .word 0 /* Reserved */ 80 .word 0 /* Reserved */ 81 .word 0 /* Reserved */ 82 .word 0 /* Reserved */ 83 .word SVC_Handler /* SVCall Handler */ 84 .word DebugMon_Handler /* Debug Monitor Handler */ 85 .word 0 /* Reserved */ 86 .word PendSV_Handler /* PendSV Handler */ 87 .word OS_CPU_SysTickHandler /* SysTick Handler */ 88 89 /* External interrupts */ 90 .word SDIO_RX_IRQHandler 91 .word SDIO_TX_IRQHandler 92 .word SDIO_RX_CMD_IRQHandler 93 .word SDIO_TX_CMD_IRQHandler 94 .word tls_wl_mac_isr 95 .word Default_Handler 96 .word tls_wl_rx_isr 97 .word tls_wl_mgmt_tx_isr 98 .word tls_wl_data_tx_isr 99 .word PMU_TIMER1_IRQHandler 100 .word PMU_TIMER0_IRQHandler 101 .word PMU_GPIO_WAKE_IRQHandler 102 .word PMU_SDIO_WAKE_IRQHandler 103 .word DMA_Channel0_IRQHandler 104 .word DMA_Channel1_IRQHandler 105 .word DMA_Channel2_IRQHandler 106 .word DMA_Channel3_IRQHandler 107 .word DMA_Channel4_7_IRQHandler 108 .word DMA_BRUST_IRQHandler 109 .word I2C_IRQHandler 110 .word ADC_IRQHandler 111 .word SPI_LS_IRQHandler 112 .word SPI_HS_IRQHandler 113 .word UART0_IRQHandler 114 .word UART1_IRQHandler 115 .word GPIOA_IRQHandler 116 .word TIM0_IRQHandler 117 .word TIM1_IRQHandler 118 .word TIM2_IRQHandler 119 .word TIM3_IRQHandler 120 .word TIM4_IRQHandler 121 .word TIM5_IRQHandler 122 .word WDG_IRQHandler 123 .word PMU_IRQHandler 124 .word FLASH_IRQHandler 125 .word PWM_IRQHandler 126 .word I2S_IRQHandler 127 .word PMU_RTC_IRQHandler 128 .word RSA_IRQHandler 129 .word CRYPTION_IRQHandler 130 .word GPIOB_IRQHandler 131 .word UART2_IRQHandler 132 133 .size __isr_vector, . - __isr_vector 134 135 .text 136 .thumb 137 .thumb_func 138 .align 2 139 .globl Reset_Handler 140 .type Reset_Handler, %function 141Reset_Handler: 142 143/* Firstly it copies data from read only memory to RAM. 144 * 145 * The ranges of copy from/to are specified by following symbols 146 * __etext: LMA of start of the section to copy from. Usually end of text 147 * __data_start__: VMA of start of the section to copy to 148 * __data_end__: VMA of end of the section to copy to 149 * 150 * All addresses must be aligned to 4 bytes boundary. 151 */ 152 ldr r1, =__etext 153 ldr r2, =__data_start__ 154 ldr r3, =__data_end__ 155 156.L_loop1: 157 cmp r2, r3 158 ittt lt 159 ldrlt r0, [r1], #4 160 strlt r0, [r2], #4 161 blt .L_loop1 162 163/* Single BSS section scheme. 164 * 165 * The BSS section is specified by following symbols 166 * __bss_start__: start of the BSS section. 167 * __bss_end__: end of the BSS section. 168 * 169 * Both addresses must be aligned to 4 bytes boundary. 170 */ 171 ldr r1, =__bss_start__ 172 ldr r2, =__bss_end__ 173 174 movs r0, 0 175.L_loop2: 176 cmp r1, r2 177 itt lt 178 strlt r0, [r1], #4 179 blt .L_loop2 180 181#ifndef __NO_SYSTEM_INIT 182 bl SystemInit 183#endif 184 185 bl main 186 187 .pool 188 .size Reset_Handler, . - Reset_Handler 189 190 .align 1 191 .thumb_func 192 .weak Default_Handler 193 .type Default_Handler, %function 194Default_Handler: 195 b . 196 .size Default_Handler, . - Default_Handler 197 198/* Macro to define default handlers. Default handler 199 * will be weak symbol and just dead loops. They can be 200 * overwritten by other handlers */ 201 .macro def_irq_handler handler_name 202 .weak \handler_name 203 .set \handler_name, Default_Handler 204 .endm 205 206 def_irq_handler NMI_Handler 207 def_irq_handler HardFault_Handler 208 def_irq_handler MemManage_Handler 209 def_irq_handler BusFault_Handler 210 def_irq_handler UsageFault_Handler 211 def_irq_handler SVC_Handler 212 def_irq_handler DebugMon_Handler 213 def_irq_handler PendSV_Handler 214 def_irq_handler OS_CPU_SysTickHandler 215 216 def_irq_handler SDIO_RX_IRQHandler 217 def_irq_handler SDIO_TX_IRQHandler 218 def_irq_handler SDIO_RX_CMD_IRQHandler 219 def_irq_handler SDIO_TX_CMD_IRQHandler 220 def_irq_handler tls_wl_mac_isr 221 def_irq_handler tls_wl_rx_isr 222 def_irq_handler tls_wl_mgmt_tx_isr 223 def_irq_handler tls_wl_data_tx_isr 224 def_irq_handler PMU_TIMER1_IRQHandler 225 def_irq_handler PMU_TIMER0_IRQHandler 226 def_irq_handler PMU_GPIO_WAKE_IRQHandler 227 def_irq_handler PMU_SDIO_WAKE_IRQHandler 228 def_irq_handler DMA_Channel0_IRQHandler 229 def_irq_handler DMA_Channel1_IRQHandler 230 def_irq_handler DMA_Channel2_IRQHandler 231 def_irq_handler DMA_Channel3_IRQHandler 232 def_irq_handler DMA_Channel4_7_IRQHandler 233 def_irq_handler DMA_BRUST_IRQHandler 234 def_irq_handler I2C_IRQHandler 235 def_irq_handler ADC_IRQHandler 236 def_irq_handler SPI_LS_IRQHandler 237 def_irq_handler SPI_HS_IRQHandler 238 def_irq_handler UART0_IRQHandler 239 def_irq_handler UART1_IRQHandler 240 def_irq_handler GPIOA_IRQHandler 241 def_irq_handler TIM0_IRQHandler 242 def_irq_handler TIM1_IRQHandler 243 def_irq_handler TIM2_IRQHandler 244 def_irq_handler TIM3_IRQHandler 245 def_irq_handler TIM4_IRQHandler 246 def_irq_handler TIM5_IRQHandler 247 def_irq_handler WDG_IRQHandler 248 def_irq_handler PMU_IRQHandler 249 def_irq_handler FLASH_IRQHandler 250 def_irq_handler PWM_IRQHandler 251 def_irq_handler I2S_IRQHandler 252 def_irq_handler PMU_RTC_IRQHandler 253 def_irq_handler RSA_IRQHandler 254 def_irq_handler CRYPTION_IRQHandler 255 def_irq_handler GPIOB_IRQHandler 256 def_irq_handler UART2_IRQHandler 257 258 .end 259