1 /* 2 * Copyright (C) 2015-2020 Alibaba Group Holding Limited 3 */ 4 #ifndef __REG_BTCMU_BEST2001_H__ 5 #define __REG_BTCMU_BEST2001_H__ 6 7 #include "plat_types.h" 8 9 struct BTCMU_T { 10 __IO uint32_t CLK_ENABLE; // 0x00 11 __IO uint32_t CLK_DISABLE; // 0x04 12 __IO uint32_t CLK_MODE; // 0x08 13 __IO uint32_t DIV_TIMER; // 0x0C 14 __IO uint32_t RESET_SET; // 0x10 15 __IO uint32_t RESET_CLR; // 0x14 16 __IO uint32_t DIV_WDT; // 0x18 17 __IO uint32_t RESET_PULSE; // 0x1C 18 uint32_t RESERVED_020[0x24 / 4]; // 0x20 19 __IO uint32_t CLK_OUT; // 0x44 20 uint32_t RESERVED_048[2]; // 0x48 21 __IO uint32_t ISIRQ_SET; // 0x50 22 __IO uint32_t ISIRQ_CLR; // 0x54 23 }; 24 25 // reg_44 26 #define BT_CMU_CAL_TIME(n) (((n) & 0xFF) << 0) 27 #define BT_CMU_CAL_TIME_MASK (0xFF << 0) 28 #define BT_CMU_CAL_TIME_SHIFT (0) 29 #define BT_CMU_SMP_CMU_SEL(n) (((n) & 0xF) << 8) 30 #define BT_CMU_SMP_CMU_SEL_MASK (0xF << 8) 31 #define BT_CMU_SMP_CMU_SEL_SHIFT (8) 32 #define BT_CMU_CFG_CLK_OUT(n) (((n) & 0xF) << 12) 33 #define BT_CMU_CFG_CLK_OUT_MASK (0xF << 12) 34 #define BT_CMU_CFG_CLK_OUT_SHIFT (12) 35 #define BT_CMU_PWR_DELAY(n) (((n) & 0x7F) << 16) 36 #define BT_CMU_PWR_DELAY_MASK (0x7F << 16) 37 #define BT_CMU_PWR_DELAY_SHIFT (16) 38 #define BT_CMU_ROM_PGEN(n) (((n) & 0xF) << 23) 39 #define BT_CMU_ROM_PGEN_MASK (0xF << 23) 40 #define BT_CMU_ROM_PGEN_SHIFT (23) 41 #define BT_CMU_RAM_EMAS (1 << 27) 42 #define BT_CMU_RF_EMAS (1 << 28) 43 44 #endif 45 46