1 /*
2 * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3 */
4 #ifndef __HAL_BTPCMIP_H__
5 #define __HAL_BTPCMIP_H__
6
7 #ifdef __cplusplus
8 extern "C" {
9 #endif
10
11 #include "plat_types.h"
12 #include "reg_btpcmip.h"
13
14 #define btpcmip_read32(b,a) \
15 (*(volatile uint32_t *)(b+a))
16
17 #define btpcmip_write32(v,b,a) \
18 ((*(volatile uint32_t *)(b+a)) = v)
19
btpcmip_w_enable_btpcmip(uint32_t reg_base,uint32_t v)20 static inline void btpcmip_w_enable_btpcmip(uint32_t reg_base, uint32_t v)
21 {
22 uint32_t val = 0;
23
24 val = btpcmip_read32(reg_base, BTPCMIP_ENABLE_REG_REG_OFFSET);
25 if (v)
26 val |= BTPCMIP_ENABLE_REG_BTPCM_ENABLE_MASK;
27 else
28 val &= ~BTPCMIP_ENABLE_REG_BTPCM_ENABLE_MASK;
29
30 btpcmip_write32(val, reg_base, BTPCMIP_ENABLE_REG_REG_OFFSET);
31 }
32
btpcmip_flush_rx_fifo(uint32_t reg_base)33 static inline void btpcmip_flush_rx_fifo(uint32_t reg_base)
34 {
35 uint32_t val = 0;
36 val = btpcmip_read32(reg_base, BTPCMIP_RX_FIFO_FLUSH_REG_OFFSET);
37
38 val |= BTPCMIP_RX_FIFO_FLUSH_MASK;
39
40 val &= ~BTPCMIP_RX_FIFO_FLUSH_MASK;
41
42 btpcmip_write32(val, reg_base, BTPCMIP_RX_FIFO_FLUSH_REG_OFFSET);
43 }
44
btpcmip_flush_tx_fifo(uint32_t reg_base)45 static inline void btpcmip_flush_tx_fifo(uint32_t reg_base)
46 {
47 uint32_t val = 0;
48 val = btpcmip_read32(reg_base, BTPCMIP_TX_FIFO_FLUSH_REG_OFFSET);
49
50 val |= BTPCMIP_TX_FIFO_FLUSH_MASK;
51
52 val &= ~BTPCMIP_TX_FIFO_FLUSH_MASK;
53
54 btpcmip_write32(val, reg_base, BTPCMIP_TX_FIFO_FLUSH_REG_OFFSET);
55 }
56
btpcmip_w_tx_fifo(uint32_t reg_base,uint32_t v)57 static inline void btpcmip_w_tx_fifo(uint32_t reg_base, uint32_t v)
58 {
59 btpcmip_write32(v, reg_base, BTPCMIP_TX_BUFF_REG_OFFSET);
60 }
61
62 ////config btpcm parameter
btpcmip_w_shortsync(uint32_t reg_base,uint32_t v)63 static inline void btpcmip_w_shortsync(uint32_t reg_base, uint32_t v)
64 {
65 uint32_t val = 0;
66 val = btpcmip_read32(reg_base, BTPCMIP_CR_REG_OFFSET);
67 if (v)
68 val |= BTPCMIP_CR_SYNCSHORT_MASK;
69 else
70 val &= ~BTPCMIP_CR_SYNCSHORT_MASK;
71 btpcmip_write32(val, reg_base, BTPCMIP_CR_REG_OFFSET);
72 }
73
btpcmip_w_length(uint32_t reg_base,uint32_t v)74 static inline void btpcmip_w_length(uint32_t reg_base, uint32_t v)
75 {
76 uint32_t val = 0;
77 val = btpcmip_read32(reg_base, BTPCMIP_CR_REG_OFFSET);
78 val &= ~BTPCMIP_CR_LENTH_MASK;
79 val |= (BTPCMIP_CR_LENTH_MASK & (v << BTPCMIP_CR_LENTH_SHIFT));
80 btpcmip_write32(val, reg_base, BTPCMIP_CR_REG_OFFSET);
81 }
82
btpcmip_w_slot_sel(uint32_t reg_base,uint32_t v)83 static inline void btpcmip_w_slot_sel(uint32_t reg_base, uint32_t v)
84 {
85 uint32_t val = 0;
86 val = btpcmip_read32(reg_base, BTPCMIP_CR_REG_OFFSET);
87 val &= ~BTPCMIP_CR_SLOTSEL_MASK;
88 val |= v;
89 btpcmip_write32(val, reg_base, BTPCMIP_CR_REG_OFFSET);
90 }
91
btpcmip_pcm_clk_open_en(uint32_t reg_base,uint32_t v)92 static inline void btpcmip_pcm_clk_open_en(uint32_t reg_base, uint32_t v)
93 {
94 uint32_t val = 0;
95 val = btpcmip_read32(reg_base, BTPCMIP_CR_REG_OFFSET);
96 val &= ~BTPCMIP_CR_PCM_CLK_OPEN_EN_MASK;
97 val |= v<<BTPCMIP_CR_PCM_CLK_OPEN_EN_SHIFT;
98 btpcmip_write32(val, reg_base, BTPCMIP_CR_REG_OFFSET);
99 }
100
btpcmip_w_mask1mask2(uint32_t reg_base,uint32_t v)101 static inline void btpcmip_w_mask1mask2(uint32_t reg_base, uint32_t v)
102 {
103 uint32_t val = 0;
104 val = btpcmip_read32(reg_base, BTPCMIP_CR_REG_OFFSET);
105 val &= ~BTPCMIP_CR_MASK1_MASK;
106 val &= ~BTPCMIP_CR_MASK2_MASK;
107 val |= BTPCMIP_CR_MASK1_MASK;
108 val |= BTPCMIP_CR_MASK2_MASK;
109 btpcmip_write32(val, reg_base, BTPCMIP_CR_REG_OFFSET);
110 }
111
112 ////config rx parameter
btpcmip_w_signextin(uint32_t reg_base,uint32_t v)113 static inline void btpcmip_w_signextin(uint32_t reg_base, uint32_t v)
114 {
115 uint32_t val = 0;
116 val = btpcmip_read32(reg_base, BTPCMIP_RCR0_REG_OFFSET);
117 if (v)
118 val |= BTPCMIP_RCR0_SIGNEXTIN_MASK;
119 else
120 val &= ~BTPCMIP_RCR0_SIGNEXTIN_MASK;
121 btpcmip_write32(val, reg_base, BTPCMIP_RCR0_REG_OFFSET);
122 }
123
btpcmip_w_msbin(uint32_t reg_base,uint32_t v)124 static inline void btpcmip_w_msbin(uint32_t reg_base, uint32_t v)
125 {
126 uint32_t val = 0;
127 val = btpcmip_read32(reg_base, BTPCMIP_RCR0_REG_OFFSET);
128 if (v)
129 val |= BTPCMIP_RCR0_MSBIN_MASK;
130 else
131 val &= ~BTPCMIP_RCR0_MSBIN_MASK;
132 btpcmip_write32(val, reg_base, BTPCMIP_RCR0_REG_OFFSET);
133 }
134
btpcmip_w_signin(uint32_t reg_base,uint32_t v)135 static inline void btpcmip_w_signin(uint32_t reg_base, uint32_t v)
136 {
137 uint32_t val = 0;
138 val = btpcmip_read32(reg_base, BTPCMIP_RCR0_REG_OFFSET);
139 if (v)
140 val |= BTPCMIP_RCR0_SIGNIN_MASK;
141 else
142 val &= ~BTPCMIP_RCR0_SIGNIN_MASK;
143 btpcmip_write32(val, reg_base, BTPCMIP_RCR0_REG_OFFSET);
144 }
145
btpcmip_w_2sin(uint32_t reg_base,uint32_t v)146 static inline void btpcmip_w_2sin(uint32_t reg_base, uint32_t v)
147 {
148 uint32_t val = 0;
149 val = btpcmip_read32(reg_base, BTPCMIP_RCR0_REG_OFFSET);
150 if (v)
151 val |= BTPCMIP_RCR0_2SIN_MASK;
152 else
153 val &= ~BTPCMIP_RCR0_2SIN_MASK;
154 btpcmip_write32(val, reg_base, BTPCMIP_RCR0_REG_OFFSET);
155 }
156
btpcmip_w_1sin(uint32_t reg_base,uint32_t v)157 static inline void btpcmip_w_1sin(uint32_t reg_base, uint32_t v)
158 {
159 uint32_t val = 0;
160 val = btpcmip_read32(reg_base, BTPCMIP_RCR0_REG_OFFSET);
161 if (v)
162 val |= BTPCMIP_RCR0_1SIN_MASK;
163 else
164 val &= ~BTPCMIP_RCR0_1SIN_MASK;
165 btpcmip_write32(val, reg_base, BTPCMIP_RCR0_REG_OFFSET);
166 }
167
168 ////config tx parameter
btpcmip_w_signexto(uint32_t reg_base,uint32_t v)169 static inline void btpcmip_w_signexto(uint32_t reg_base, uint32_t v)
170 {
171 uint32_t val = 0;
172 val = btpcmip_read32(reg_base, BTPCMIP_TCR0_REG_OFFSET);
173 if (v)
174 val |= BTPCMIP_TCR0_SIGNEXTO_MASK;
175 else
176 val &= ~BTPCMIP_TCR0_SIGNEXTO_MASK;
177 btpcmip_write32(val, reg_base, BTPCMIP_TCR0_REG_OFFSET);
178 }
179
btpcmip_w_msbo(uint32_t reg_base,uint32_t v)180 static inline void btpcmip_w_msbo(uint32_t reg_base, uint32_t v)
181 {
182 uint32_t val = 0;
183 val = btpcmip_read32(reg_base, BTPCMIP_TCR0_REG_OFFSET);
184 if (v)
185 val |= BTPCMIP_TCR0_MSBO_MASK;
186 else
187 val &= ~BTPCMIP_TCR0_MSBO_MASK;
188 btpcmip_write32(val, reg_base, BTPCMIP_TCR0_REG_OFFSET);
189 }
190
btpcmip_w_signo(uint32_t reg_base,uint32_t v)191 static inline void btpcmip_w_signo(uint32_t reg_base, uint32_t v)
192 {
193 uint32_t val = 0;
194 val = btpcmip_read32(reg_base, BTPCMIP_TCR0_REG_OFFSET);
195 if (v)
196 val |= BTPCMIP_TCR0_SIGNO_MASK;
197 else
198 val &= ~BTPCMIP_TCR0_SIGNO_MASK;
199 btpcmip_write32(val, reg_base, BTPCMIP_TCR0_REG_OFFSET);
200 }
201
btpcmip_w_2so(uint32_t reg_base,uint32_t v)202 static inline void btpcmip_w_2so(uint32_t reg_base, uint32_t v)
203 {
204 uint32_t val = 0;
205 val = btpcmip_read32(reg_base, BTPCMIP_TCR0_REG_OFFSET);
206 if (v)
207 val |= BTPCMIP_TCR0_2SO_MASK;
208 else
209 val &= ~BTPCMIP_TCR0_2SO_MASK;
210 btpcmip_write32(val, reg_base, BTPCMIP_TCR0_REG_OFFSET);
211 }
212
btpcmip_w_1so(uint32_t reg_base,uint32_t v)213 static inline void btpcmip_w_1so(uint32_t reg_base, uint32_t v)
214 {
215 uint32_t val = 0;
216 val = btpcmip_read32(reg_base, BTPCMIP_TCR0_REG_OFFSET);
217 if (v)
218 val |= BTPCMIP_TCR0_1SO_MASK;
219 else
220 val &= ~BTPCMIP_TCR0_1SO_MASK;
221 btpcmip_write32(val, reg_base, BTPCMIP_TCR0_REG_OFFSET);
222 }
223
224 ////
btpcmip_r_int_status(uint32_t reg_base)225 static inline uint32_t btpcmip_r_int_status(uint32_t reg_base)
226 {
227 return btpcmip_read32(reg_base, BTPCMIP_INT_STATUS_REG_OFFSET);
228 }
229
230 ////
btpcmip_w_tx_fifo_threshold(uint32_t reg_base,uint32_t v)231 static inline void btpcmip_w_tx_fifo_threshold(uint32_t reg_base, uint32_t v)
232 {
233 btpcmip_write32(v<<BTPCMIP_TX_FIFO_CFG_LEVEL_SHIFT, reg_base, BTPCMIP_TX_FIFO_CFG_REG_OFFSET);
234 }
btpcmip_w_rx_fifo_threshold(uint32_t reg_base,uint32_t v)235 static inline void btpcmip_w_rx_fifo_threshold(uint32_t reg_base, uint32_t v)
236 {
237 btpcmip_write32(v<<BTPCMIP_RX_FIFO_CFG_LEVEL_SHIFT, reg_base, BTPCMIP_RX_FIFO_CFG_REG_OFFSET);
238 }
239
btpcmip_w_enable_tx_dma(uint32_t reg_base,uint32_t v)240 static inline void btpcmip_w_enable_tx_dma(uint32_t reg_base, uint32_t v)
241 {
242 uint32_t val = 0;
243 val = btpcmip_read32(reg_base, BTPCMIP_DMA_CTRL_REG_OFFSET);
244 if (v)
245 val |= BTPCMIP_DMA_CTRL_TX_ENABLE_MASK;
246 else
247 val &= ~BTPCMIP_DMA_CTRL_TX_ENABLE_MASK;
248
249 btpcmip_write32(val, reg_base, BTPCMIP_DMA_CTRL_REG_OFFSET);
250 }
btpcmip_w_enable_rx_dma(uint32_t reg_base,uint32_t v)251 static inline void btpcmip_w_enable_rx_dma(uint32_t reg_base, uint32_t v)
252 {
253 uint32_t val = 0;
254 val = btpcmip_read32(reg_base, BTPCMIP_DMA_CTRL_REG_OFFSET);
255 if (v)
256 val |= BTPCMIP_DMA_CTRL_RX_ENABLE_MASK;
257 else
258 val &= ~BTPCMIP_DMA_CTRL_RX_ENABLE_MASK;
259
260 btpcmip_write32(val, reg_base, BTPCMIP_DMA_CTRL_REG_OFFSET);
261 }
262
263 #ifdef __cplusplus
264 }
265 #endif
266
267 #endif /* __HAL_BTPCMIP_H__ */
268