1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef __HAL_I2SIP_H__
5 #define __HAL_I2SIP_H__
6 
7 #ifdef __cplusplus
8 extern "C" {
9 #endif
10 
11 #include "plat_types.h"
12 #include "reg_i2sip.h"
13 
14 #define i2sip_read32(b,a) \
15      (*(volatile uint32_t *)(b+a))
16 
17 #define i2sip_write32(v,b,a) \
18      ((*(volatile uint32_t *)(b+a)) = v)
19 
i2sip_w_enable_i2sip(uint32_t reg_base,uint32_t v)20 static inline void i2sip_w_enable_i2sip(uint32_t reg_base, uint32_t v)
21 {
22     uint32_t val = 0;
23 
24     val = i2sip_read32(reg_base, I2SIP_ENABLE_REG_REG_OFFSET);
25     if (v)
26         val |= I2SIP_ENABLE_REG_I2S_ENABLE_MASK;
27     else
28         val &= ~I2SIP_ENABLE_REG_I2S_ENABLE_MASK;
29 
30     i2sip_write32(val, reg_base, I2SIP_ENABLE_REG_REG_OFFSET);
31 }
32 #ifndef CHIP_BEST1000
i2sip_w_enable_slave_mode(uint32_t reg_base,uint32_t v)33 static inline void i2sip_w_enable_slave_mode(uint32_t reg_base, uint32_t v)
34 {
35     uint32_t val = 0;
36 
37     val = i2sip_read32(reg_base, I2SIP_ENABLE_REG_REG_OFFSET);
38     if (v)
39         val |= I2SIP_ENABLE_REG_SLAVE_MODE_MASK;
40     else
41         val &= ~I2SIP_ENABLE_REG_SLAVE_MODE_MASK;
42 
43     i2sip_write32(val, reg_base, I2SIP_ENABLE_REG_REG_OFFSET);
44 }
45 #endif
i2sip_w_enable_clk_gen(uint32_t reg_base,uint32_t v)46 static inline void i2sip_w_enable_clk_gen(uint32_t reg_base, uint32_t v)
47 {
48     if (v)
49         i2sip_write32(1, reg_base, I2SIP_CLK_GEN_ENABLE_REG_REG_OFFSET);
50     else
51         i2sip_write32(0, reg_base, I2SIP_CLK_GEN_ENABLE_REG_REG_OFFSET);
52 }
i2sip_r_clk_gen_enabled(uint32_t reg_base)53 static inline uint32_t i2sip_r_clk_gen_enabled(uint32_t reg_base)
54 {
55     uint32_t v;
56 
57     v = i2sip_read32(reg_base, I2SIP_CLK_GEN_ENABLE_REG_REG_OFFSET);
58     return !!(v & I2SIP_CLK_GEN_ENABLE_REG_ENABLE_MASK);
59 }
i2sip_w_enable_rx_block(uint32_t reg_base,uint32_t v)60 static inline void i2sip_w_enable_rx_block(uint32_t reg_base, uint32_t v)
61 {
62     if (v)
63         i2sip_write32(1, reg_base, I2SIP_RX_BLOCK_ENABLE_REG_REG_OFFSET);
64     else
65         i2sip_write32(0, reg_base, I2SIP_RX_BLOCK_ENABLE_REG_REG_OFFSET);
66 }
i2sip_w_enable_rx_channel(uint32_t reg_base,uint32_t chan,uint32_t v)67 static inline void i2sip_w_enable_rx_channel(uint32_t reg_base, uint32_t chan, uint32_t v)
68 {
69     if (v)
70         i2sip_write32(1, reg_base, I2SIP_RX_ENABLE_REG_OFFSET(chan));
71     else
72         i2sip_write32(0, reg_base, I2SIP_RX_ENABLE_REG_OFFSET(chan));
73 }
i2sip_w_enable_tx_block(uint32_t reg_base,uint32_t v)74 static inline void i2sip_w_enable_tx_block(uint32_t reg_base, uint32_t v)
75 {
76     if (v)
77         i2sip_write32(1, reg_base, I2SIP_TX_BLOCK_ENABLE_REG_REG_OFFSET);
78     else
79         i2sip_write32(0, reg_base, I2SIP_TX_BLOCK_ENABLE_REG_REG_OFFSET);
80 }
i2sip_w_enable_tx_channel(uint32_t reg_base,uint32_t chan,uint32_t v)81 static inline void i2sip_w_enable_tx_channel(uint32_t reg_base, uint32_t chan, uint32_t v)
82 {
83     if (v)
84         i2sip_write32(1, reg_base, I2SIP_TX_ENABLE_REG_OFFSET(chan));
85     else
86         i2sip_write32(0, reg_base, I2SIP_TX_ENABLE_REG_OFFSET(chan));
87 }
i2sip_w_tx_resolution(uint32_t reg_base,uint32_t chan,uint32_t v)88 static inline void i2sip_w_tx_resolution(uint32_t reg_base, uint32_t chan, uint32_t v)
89 {
90     i2sip_write32(v<<I2SIP_TX_CFG_WLEN_SHIFT, reg_base, I2SIP_TX_CFG_REG_OFFSET(chan));
91 }
i2sip_w_rx_resolution(uint32_t reg_base,uint32_t chan,uint32_t v)92 static inline void i2sip_w_rx_resolution(uint32_t reg_base, uint32_t chan, uint32_t v)
93 {
94     i2sip_write32(v<<I2SIP_RX_CFG_WLEN_SHIFT, reg_base, I2SIP_RX_CFG_REG_OFFSET(chan));
95 }
i2sip_w_clk_cfg_reg(uint32_t reg_base,uint32_t v)96 static inline void i2sip_w_clk_cfg_reg(uint32_t reg_base, uint32_t v)
97 {
98     i2sip_write32(v, reg_base, I2SIP_CLK_CFG_REG_OFFSET);
99 }
i2sip_w_tx_left_fifo(uint32_t reg_base,uint32_t chan,uint32_t v)100 static inline void i2sip_w_tx_left_fifo(uint32_t reg_base, uint32_t chan, uint32_t v)
101 {
102     i2sip_write32(v, reg_base, I2SIP_LEFT_TX_BUFF_REG_OFFSET(chan));
103 }
i2sip_w_tx_right_fifo(uint32_t reg_base,uint32_t chan,uint32_t v)104 static inline void i2sip_w_tx_right_fifo(uint32_t reg_base, uint32_t chan, uint32_t v)
105 {
106     i2sip_write32(v, reg_base, I2SIP_RIGHT_TX_BUFF_REG_OFFSET(chan));
107 }
i2sip_w_tx_fifo_threshold(uint32_t reg_base,uint32_t chan,uint32_t v)108 static inline void i2sip_w_tx_fifo_threshold(uint32_t reg_base, uint32_t chan, uint32_t v)
109 {
110     i2sip_write32(v<<I2SIP_TX_FIFO_CFG_LEVEL_SHIFT, reg_base, I2SIP_TX_FIFO_CFG_REG_OFFSET(chan));
111 }
i2sip_w_rx_fifo_threshold(uint32_t reg_base,uint32_t chan,uint32_t v)112 static inline void i2sip_w_rx_fifo_threshold(uint32_t reg_base, uint32_t chan, uint32_t v)
113 {
114     i2sip_write32(v<<I2SIP_RX_FIFO_CFG_LEVEL_SHIFT, reg_base, I2SIP_RX_FIFO_CFG_REG_OFFSET(chan));
115 }
i2sip_w_tx_fifo_reset(uint32_t reg_base,uint32_t chan)116 static inline void i2sip_w_tx_fifo_reset(uint32_t reg_base, uint32_t chan)
117 {
118     i2sip_write32(I2SIP_TX_FIFO_FLUSH_MASK, reg_base, I2SIP_TX_FIFO_FLUSH_REG_OFFSET(chan));
119 }
i2sip_w_rx_fifo_reset(uint32_t reg_base,uint32_t chan)120 static inline void i2sip_w_rx_fifo_reset(uint32_t reg_base, uint32_t chan)
121 {
122     i2sip_write32(I2SIP_RX_FIFO_FLUSH_MASK, reg_base, I2SIP_RX_FIFO_FLUSH_REG_OFFSET(chan));
123 }
i2sip_r_int_status(uint32_t reg_base,uint32_t chan)124 static inline uint32_t i2sip_r_int_status(uint32_t reg_base, uint32_t chan)
125 {
126     return i2sip_read32(reg_base, I2SIP_INT_STATUS_REG_OFFSET(chan));
127 }
i2sip_w_enable_tx_dma(uint32_t reg_base,uint32_t v)128 static inline void i2sip_w_enable_tx_dma(uint32_t reg_base, uint32_t v)
129 {
130     uint32_t val = 0;
131     val = i2sip_read32(reg_base, I2SIP_DMA_CTRL_REG_OFFSET);
132     if (v)
133         val |= I2SIP_DMA_CTRL_TX_ENABLE_MASK;
134     else
135         val &= ~I2SIP_DMA_CTRL_TX_ENABLE_MASK;
136 
137     i2sip_write32(val, reg_base, I2SIP_DMA_CTRL_REG_OFFSET);
138 }
i2sip_w_enable_rx_dma(uint32_t reg_base,uint32_t v)139 static inline void i2sip_w_enable_rx_dma(uint32_t reg_base, uint32_t v)
140 {
141     uint32_t val = 0;
142     val = i2sip_read32(reg_base, I2SIP_DMA_CTRL_REG_OFFSET);
143     if (v)
144         val |= I2SIP_DMA_CTRL_RX_ENABLE_MASK;
145     else
146         val &= ~I2SIP_DMA_CTRL_RX_ENABLE_MASK;
147 
148     i2sip_write32(val, reg_base, I2SIP_DMA_CTRL_REG_OFFSET);
149 }
150 #ifndef CHIP_BEST1000
i2sp_w_enable_rx_dma_block(uint32_t reg_base,uint32_t v)151 static inline void i2sp_w_enable_rx_dma_block(uint32_t reg_base, uint32_t v)
152 {
153     uint32_t val = 0;
154     val = i2sip_read32(reg_base, I2SIP_DMA_CTRL_REG_OFFSET);
155     if (v)
156         val |= I2SIP_DMA_CTRL_RX_DMA_BLK_EN_MASK;
157     else
158         val &= ~I2SIP_DMA_CTRL_RX_DMA_BLK_EN_MASK;
159 
160     i2sip_write32(val, reg_base, I2SIP_DMA_CTRL_REG_OFFSET);
161 }
i2sip_w_rx_dma_blk_size(uint32_t reg_base,uint32_t v)162 static inline void i2sip_w_rx_dma_blk_size(uint32_t reg_base, uint32_t v)
163 {
164     uint32_t val = 0;
165     val = i2sip_read32(reg_base, I2SIP_DMA_CTRL_REG_OFFSET);
166     val = SET_BITFIELD(val, I2SIP_DMA_CTRL_RX_DMA_BLK_SIZE, v);
167     i2sip_write32(val, reg_base, I2SIP_DMA_CTRL_REG_OFFSET);
168 }
169 #endif
170 #ifdef __cplusplus
171 }
172 #endif
173 
174 #endif /* __HAL_I2SIP_H__ */
175