1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef __HAL_TDM_H__
5 #define __HAL_TDM_H__
6 
7 #ifdef __cplusplus
8 extern "C" {
9 #endif
10 
11 #include "reg_tdm.h"
12 #include "hal_i2s.h"
13 
14 #define TDM_BUF_ALIGN __attribute__((aligned(0x100)))
15 
16 enum HAL_TDM_ENABLE_T {
17     HAL_TDM_DISABLE,
18     HAL_TDM_ENABLE,
19     HAL_TDM_ENABLE_NUM,
20 };
21 
22 enum HAL_TDM_MODE_T {
23     HAL_TDM_MODE_FS_ASSERTED_AT_FIRST,
24     HAL_TDM_MODE_FS_ASSERTED_AT_LAST,
25     HAL_TDM_MODE_NUM,
26 };
27 
28 enum HAL_TDM_FS_EDGE_T {
29     HAL_TDM_FS_EDGE_POSEDGE,
30     HAL_TDM_FS_EDGE_NEGEDGE,
31     HAL_TDM_FS_EDGE_NUM,
32 };
33 
34 enum HAL_TDM_CYCLES_T {
35     HAL_TDM_CYCLES_16     = 16,
36     HAL_TDM_CYCLES_32     = 32,
37     HAL_TDM_CYCLES_64     = 64,
38     HAL_TDM_CYCLES_128    = 128,
39     HAL_TDM_CYCLES_256    = 256,
40     HAL_TDM_CYCLES_512    = 512,
41 };
42 
43 enum HAL_TDM_FS_CYCLES {
44     HAL_TDM_FS_CYCLES_ONE_LESS = 0,
45     HAL_TDM_FS_CYCLES_1     = 1,
46     HAL_TDM_FS_CYCLES_8    = 8,
47     HAL_TDM_FS_CYCLES_16   = 16,
48     HAL_TDM_FS_CYCLES_32   = 32,
49     HAL_TDM_FS_CYCLES_64   = 64,
50     HAL_TDM_FS_CYCLES_128  = 128,
51     HAL_TDM_FS_CYCLES_256  = 256,
52 };
53 
54 enum HAL_TDM_SLOT_CYCLES_T {
55     HAL_TDM_SLOT_CYCLES_32 = 32,
56     HAL_TDM_SLOT_CYCLES_16 = 16,
57 };
58 
59 struct HAL_TDM_CONFIG_T {
60     enum HAL_TDM_MODE_T mode;
61     enum HAL_TDM_FS_EDGE_T edge;
62     enum HAL_TDM_CYCLES_T cycles;
63     enum HAL_TDM_FS_CYCLES fs_cycles;
64     enum HAL_TDM_SLOT_CYCLES_T slot_cycles;
65     uint32_t data_offset;
66     bool master_clk_wait;
67 };
68 
69 int32_t hal_tdm_open(enum HAL_I2S_ID_T i2s_id,enum AUD_STREAM_T stream,enum HAL_I2S_MODE_T mode);
70 int32_t hal_tdm_setup_stream(enum HAL_I2S_ID_T i2s_id,
71                                        enum AUD_STREAM_T stream,
72                                        uint32_t sample_rate,
73                                        struct HAL_TDM_CONFIG_T *tdm_cfg);
74 int32_t hal_tdm_as_i2s_setup_stream(enum HAL_I2S_ID_T i2s_id,
75                                        enum AUD_STREAM_T stream,
76                                        uint32_t sample_rate);
77 int32_t hal_tdm_start_stream(enum HAL_I2S_ID_T i2s_id, enum AUD_STREAM_T stream);
78 int32_t hal_tdm_stop_stream(enum HAL_I2S_ID_T i2s_id, enum AUD_STREAM_T stream);
79 int32_t hal_tdm_close(enum HAL_I2S_ID_T i2s_id, enum AUD_STREAM_T stream);
80 void hal_tdm_get_config(enum HAL_I2S_ID_T i2s_id,struct HAL_TDM_CONFIG_T *tdm_cfg);
81 void hal_tdm_set_config(enum HAL_I2S_ID_T i2s_id,struct HAL_TDM_CONFIG_T *tdm_cfg);
82 #ifdef __cplusplus
83 }
84 #endif
85 
86 #endif // __HAL_TDM_H__