1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef __REG_BTPCMIP_H_
5 #define __REG_BTPCMIP_H_
6 
7 #include "plat_types.h"
8 
9 #define BTPCMIP_FIFO_DEPTH 8
10 
11 /* btpcmip register */
12 /* enable register */
13 #define BTPCMIP_ENABLE_REG_REG_OFFSET 0x0
14 #define BTPCMIP_ENABLE_REG_BTPCM_ENABLE_SHIFT (0)
15 #define BTPCMIP_ENABLE_REG_BTPCM_ENABLE_MASK ((0x1)<<BTPCMIP_ENABLE_REG_BTPCM_ENABLE_SHIFT)
16 
17 /* recv fifo flush register */
18 #define BTPCMIP_RX_FIFO_FLUSH_REG_OFFSET 0x4
19 #define BTPCMIP_RX_FIFO_FLUSH_SHIFT (0)
20 #define BTPCMIP_RX_FIFO_FLUSH_MASK ((0x1)<<BTPCMIP_RX_FIFO_FLUSH_SHIFT)
21 
22 /* send fifo flush register */
23 #define BTPCMIP_TX_FIFO_FLUSH_REG_OFFSET 0x8
24 #define BTPCMIP_TX_FIFO_FLUSH_SHIFT (0)
25 #define BTPCMIP_TX_FIFO_FLUSH_MASK ((0x1)<<BTPCMIP_TX_FIFO_FLUSH_SHIFT)
26 
27 /* send buffer register */
28 #define BTPCMIP_TX_BUFF_REG_OFFSET 0xc
29 
30 /* recv buffer register */
31 #define BTPCMIP_RX_BUFF_REG_OFFSET 0xc
32 
33 /* config register */
34 #define BTPCMIP_CR_REG_OFFSET 0x10
35 #define BTPCMIP_CR_MASK2_SHIFT (21)
36 #define BTPCMIP_CR_MASK2_MASK ((0x1)<<BTPCMIP_CR_MASK2_SHIFT)
37 #define BTPCMIP_CR_SYNCSHORT_SHIFT (20)
38 #define BTPCMIP_CR_SYNCSHORT_MASK ((0x1)<<BTPCMIP_CR_SYNCSHORT_SHIFT)
39 #define BTPCMIP_CR_MASK1_SHIFT (19)
40 #define BTPCMIP_CR_MASK1_MASK ((0x1)<<BTPCMIP_CR_MASK1_SHIFT)
41 #define BTPCMIP_CR_LENTH_SHIFT (16)
42 #define BTPCMIP_CR_LENTH_MASK ((0x7)<<BTPCMIP_CR_LENTH_SHIFT)
43 // Since 1302
44 #define BTPCMIP_CR_PCM_CLK_OPEN_EN_SHIFT (15)
45 #define BTPCMIP_CR_PCM_CLK_OPEN_EN_MASK ((0x1)<<BTPCMIP_CR_PCM_CLK_OPEN_EN_SHIFT)
46 // -- End of since 1302
47 #define BTPCMIP_CR_SLOTSEL_SHIFT (0)
48 #define BTPCMIP_CR_SLOTSEL_MASK ((0x7)<<BTPCMIP_CR_SLOTSEL_SHIFT)
49 
50 /* rx config register */
51 #define BTPCMIP_RCR0_REG_OFFSET 0x14
52 #define BTPCMIP_RCR0_SIGNEXTIN_SHIFT (4)
53 #define BTPCMIP_RCR0_SIGNEXTIN_MASK ((0x1)<<BTPCMIP_RCR0_SIGNEXTIN_SHIFT)
54 #define BTPCMIP_RCR0_MSBIN_SHIFT (3)
55 #define BTPCMIP_RCR0_MSBIN_MASK ((0x1)<<BTPCMIP_RCR0_MSBIN_SHIFT)
56 #define BTPCMIP_RCR0_SIGNIN_SHIFT (2)
57 #define BTPCMIP_RCR0_SIGNIN_MASK ((0x1)<<BTPCMIP_RCR0_SIGNIN_SHIFT)
58 #define BTPCMIP_RCR0_2SIN_SHIFT (1)
59 #define BTPCMIP_RCR0_2SIN_MASK ((0x1)<<BTPCMIP_RCR0_2SIN_SHIFT)
60 #define BTPCMIP_RCR0_1SIN_SHIFT (0)
61 #define BTPCMIP_RCR0_1SIN_MASK ((0x1)<<BTPCMIP_RCR0_1SIN_SHIFT)
62 
63 /* tx config register */
64 #define BTPCMIP_TCR0_REG_OFFSET 0x18
65 #define BTPCMIP_TCR0_SIGNEXTO_SHIFT (4)
66 #define BTPCMIP_TCR0_SIGNEXTO_MASK ((0x1)<<BTPCMIP_TCR0_SIGNEXTO_SHIFT)
67 #define BTPCMIP_TCR0_MSBO_SHIFT (3)
68 #define BTPCMIP_TCR0_MSBO_MASK ((0x1)<<BTPCMIP_TCR0_MSBO_SHIFT)
69 #define BTPCMIP_TCR0_SIGNO_SHIFT (2)
70 #define BTPCMIP_TCR0_SIGNO_MASK ((0x1)<<BTPCMIP_TCR0_SIGNO_SHIFT)
71 #define BTPCMIP_TCR0_2SO_SHIFT (1)
72 #define BTPCMIP_TCR0_2SO_MASK ((0x1)<<BTPCMIP_TCR0_2SO_SHIFT)
73 #define BTPCMIP_TCR0_1SO_SHIFT (0)
74 #define BTPCMIP_TCR0_1SO_MASK ((0x1)<<BTPCMIP_TCR0_1SO_SHIFT)
75 
76 /* int status register */
77 #define BTPCMIP_INT_STATUS_REG_OFFSET 0x1c
78 #define BTPCMIP_INT_STATUS_TX_FIFO_OVER_SHIFT (5)
79 #define BTPCMIP_INT_STATUS_TX_FIFO_OVER_MASK ((0x1)<<BTPCMIP_INT_STATUS_TX_FIFO_OVER_SHIFT)
80 #define BTPCMIP_INT_STATUS_TX_FIFO_EMPTY_SHIFT (4)
81 #define BTPCMIP_INT_STATUS_TX_FIFO_EMPTY_MASK ((0x1)<<BTPCMIP_INT_STATUS_TX_FIFO_EMPTY_SHIFT)
82 #define BTPCMIP_INT_STATUS_RX_FIFO_OVER_SHIFT (1)
83 #define BTPCMIP_INT_STATUS_RX_FIFO_OVER_MASK ((0x1)<<BTPCMIP_INT_STATUS_RX_FIFO_OVER_SHIFT)
84 #define BTPCMIP_INT_STATUS_RX_FIFO_DA_SHIFT (0)
85 #define BTPCMIP_INT_STATUS_RX_FIFO_DA_MASK ((0x1)<<BTPCMIP_INT_STATUS_RX_FIFO_DA_SHIFT)
86 
87 /* int mask register */
88 #define BTPCMIP_INT_MASK_REG_OFFSET 0x20
89 #define BTPCMIP_INT_MASK_TX_FIFO_OVER_SHIFT (5)
90 #define BTPCMIP_INT_MASK_TX_FIFO_OVER_MASK ((0x1)<<BTPCMIP_INT_MASK_TX_FIFO_OVER_SHIFT)
91 #define BTPCMIP_INT_MASK_TX_FIFO_EMPTY_SHIFT (4)
92 #define BTPCMIP_INT_MASK_TX_FIFO_EMPTY_MASK ((0x1)<<BTPCMIP_INT_MASK_TX_FIFO_EMPTY_SHIFT)
93 #define BTPCMIP_INT_MASK_RX_FIFO_OVER_SHIFT (1)
94 #define BTPCMIP_INT_MASK_RX_FIFO_OVER_MASK ((0x1)<<BTPCMIP_INT_MASK_RX_FIFO_OVER_SHIFT)
95 #define BTPCMIP_INT_MASK_RX_FIFO_DA_SHIFT (0)
96 #define BTPCMIP_INT_MASK_RX_FIFO_DA_MASK ((0x1)<<BTPCMIP_INT_MASK_RX_FIFO_DA_SHIFT)
97 #define BTPCMIP_INT_MASK_ALL \
98     (BTPCMIP_INT_MASK_TX_FIFO_OVER_MASK|BTPCMIP_INT_MASK_TX_FIFO_EMPTY_MASK|BTPCMIP_INT_MASK_RX_FIFO_OVER_MASK|BTPCMIP_INT_MASK_RX_FIFO_DA_MASK)
99 #define BTPCMIP_INT_UNMASK_ALL 0
100 
101 /* clr recv over flow register */
102 #define BTPCMIP_CLR_RX_OVER_FLOW_REG_OFFSET 0x24
103 #define BTPCMIP_CLR_RX_OVER_FLOW_CLR_SHIFT (0)
104 #define BTPCMIP_CLR_RX_OVER_FLOW_CLR_MASK ((0x1)<<BTPCMIP_CLR_RX_OVER_FLOW_CLR_SHIFT)
105 
106 /* clr send over flow register */
107 #define BTPCMIP_CLR_TX_OVER_FLOW_REG_OFFSET 0x28
108 #define BTPCMIP_CLR_TX_OVER_FLOW_CLR_SHIFT (0)
109 #define BTPCMIP_CLR_TX_OVER_FLOW_CLR_MASK ((0x1)<<BTPCMIP_CLR_TX_OVER_FLOW_CLR_SHIFT)
110 
111 /* recv fifo config register */
112 #define BTPCMIP_RX_FIFO_CFG_REG_OFFSET 0x2c
113 #define BTPCMIP_RX_FIFO_CFG_LEVEL_SHIFT (0)
114 #define BTPCMIP_RX_FIFO_CFG_LEVEL_MASK ((0xf)<<BTPCMIP_RX_FIFO_CFG_LEVEL_SHIFT)
115 
116 /* send fifo config register */
117 #define BTPCMIP_TX_FIFO_CFG_REG_OFFSET 0x30
118 #define BTPCMIP_TX_FIFO_CFG_LEVEL_SHIFT (0)
119 #define BTPCMIP_TX_FIFO_CFG_LEVEL_MASK ((0xf)<<BTPCMIP_TX_FIFO_CFG_LEVEL_SHIFT)
120 
121 /* dma ctrl register */
122 #define BTPCMIP_DMA_CTRL_REG_OFFSET 0x34
123 #define BTPCMIP_DMA_CTRL_TX_ENABLE_SHIFT (1)
124 #define BTPCMIP_DMA_CTRL_TX_ENABLE_MASK ((0x1)<<BTPCMIP_DMA_CTRL_TX_ENABLE_SHIFT)
125 #define BTPCMIP_DMA_CTRL_RX_ENABLE_SHIFT (0)
126 #define BTPCMIP_DMA_CTRL_RX_ENABLE_MASK ((0x1)<<BTPCMIP_DMA_CTRL_RX_ENABLE_SHIFT)
127 /* btpcmip register end */
128 
129 #endif /* __REG_BTPCMIP_H_ */
130