1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef __REG_NORFLASHIP_V1_H__
5 #define __REG_NORFLASHIP_V1_H__
6 
7 #include "plat_types.h"
8 
9 /* ip register */
10 /* 0x0 */
11 #define TX_CONFIG1_BASE 0x0
12 #define TX_ADDR_SHIFT (8)
13 #define TX_ADDR_MASK ((0xfffffff)<TX_ADDR_SHIFT)
14 #define TX_CMD_SHIFT (0)
15 #define TX_CMD_MASK ((0xFF)<TX_CMD_SHIFT)
16 #define TX_ADDR_RW_SHIFT (16)
17 #define TX_ADDR_RW_MASK ((0x1)<<TX_ADDR_RW_SHIFT)
18 
19 #define EXT_CMD_FLAG (0<<0)
20 #define EXT_CMD_SHIFT (8)
21 #define EXT_CMD_MASK (0xFF<<EXT_CMD_SHIFT)
22 #define EXT_CMD_RX_MASK (1<<16)
23 #define EXT_CMD_QUAD_MASK (1<<17)
24 
25 /* 0x4 */
26 #define TX_CONFIG2_BASE 0x4
27 #define TX_CONMOD_SHIFT (24)
28 #define TX_CONMOD_MASK ((0x1)<<TX_CONMOD_SHIFT)
29 #define TX_BLKSIZE_SHIFT (8)
30 #define TX_BLKSIZE_MASK ((0x1ff)<<TX_BLKSIZE_SHIFT)
31 #define TX_MODBIT_SHIFT (0)
32 #define TX_MODBIT_MASK ((0xff)<<TX_MODBIT_SHIFT)
33 
34 /* 0x8 */
35 #define TXDATA_BASE 0x8
36 #define TXDATA_SHIFT (0)
37 #define TXDATA_MASK ((0xff)<<TXDATA_SHIFT)
38 
39 /* 0xc */
40 #define INT_STATUS_BASE 0xc
41 #define RXFIFOCOUNT_SHIFT (4)
42 #define RXFIFOCOUNT_MASK ((0xf)<<RXFIFOCOUNT_SHIFT)
43 #define RXFIFOEMPTY_SHIFT (3)
44 #define RXFIFOEMPTY_MASK ((0x1)<<RXFIFOEMPTY_SHIFT)
45 #define TXFIFOFULL_SHIFT (2)
46 #define TXFIFOFULL_MASK ((0x1)<<TXFIFOFULL_SHIFT)
47 #define TXFIFOEMPTY_SHIFT (1)
48 #define TXFIFOEMPTY_MASK ((0x1)<<TXFIFOEMPTY_SHIFT)
49 #define BUSY_SHIFT (0)
50 #define BUSY_MASK ((0x1)<<BUSY_SHIFT)
51 
52 /* 0x10 */
53 #define RXDATA_BASE 0x10
54 #define RXDATA_SHIFT (0)
55 #define RXDATA_MASK ((0xffffffff)<<RXDATA_SHIFT)
56 
57 /* 0x14 */
58 #define MODE1_CONFIG_BASE 0x14
59 #define ADDRBYTE4_SHIFT (29)
60 #define ADDRBYTE4_MASK ((0x1)<<ADDRBYTE4_SHIFT)
61 #define RXCANCELEN_SHIFT (28)
62 #define RXCANCELEN_MASK (0x1<<RXCANCELEN_SHIFT)
63 #define WRAPTYPE_SHIFT (26)
64 #define WRAPTYPE_MASK (0x3<<WRAPTYPE_SHIFT)
65 #define WRAPEN_SHIFT (25)
66 #define WRAPEN_MASK (0x1<<WRAPEN_SHIFT)
67 #define FETCHEN_SHIFT (24)
68 #define FETCHEN_MASK (0x1<<FETCHEN_SHIFT)
69 #define DUMMYCLC_SHIFT (20)
70 #define DUMMYCLC_MASK ((0xf)<<DUMMYCLC_SHIFT)
71 #define DUMMYCLCEN_SHIFT (19)
72 #define DUMMYCLCEN_MASK ((0x1)<<DUMMYCLCEN_SHIFT)
73 #define NEG_PHASE_SHIFT (18)
74 #define NEG_PHASE_MASK ((0x1)<<NEG_PHASE_SHIFT)
75 #define POS_NEG_SHIFT (17)
76 #define POS_NEG_MASK ((0x1)<<POS_NEG_SHIFT)
77 #define CMDQUAD_SHIFT (16)
78 #define CMDQUAD_MASK ((0x1)<<CMDQUAD_SHIFT)
79 #define CLKDIV_SHIFT (8)
80 #define CLKDIV_MASK ((0xff)<<CLKDIV_SHIFT)
81 #define SAMDLY_SHIFT (4)
82 #define SAMDLY_MASK ((0x7)<<SAMDLY_SHIFT)
83 #define DUALMODE_SHIFT (3)
84 #define DUALMODE_MASK ((0x1)<<DUALMODE_SHIFT)
85 #define HOLDPIN_SHIFT (2)
86 #define HOLDPIN_MASK ((0x1)<<HOLDPIN_SHIFT)
87 #define WPRPIN_SHIFT (1)
88 #define WPRPIN_MASK ((0x1)<<WPRPIN_SHIFT)
89 #define QUADMODE_SHIFT (0)
90 #define QUADMODE_MASK ((0x1)<<QUADMODE_SHIFT)
91 
92 /* 0x18 */
93 #define FIFO_CONFIG_BASE 0x18
94 #define TXFIFOCLR_SHIFT (1)
95 #define TXFIFOCLR_MASK ((0x1)<<TXFIFOCLR_SHIFT)
96 #define RXFIFOCLR_SHIFT (0)
97 #define RXFIFOCLR_MASK ((0x1)<<RXFIFOCLR_SHIFT)
98 
99 /* 0x20 */
100 #define MODE2_CONFIG_BASE 0x20
101 #define DUALIOCMD_SHIFT (24)
102 #define DUALIOCMD_MASK ((0xff)<<DUALIOCMD_SHIFT)
103 #define RDCMD_SHIFT (16)
104 #define RDCMD_MASK ((0xff)<<RDCMD_SHIFT)
105 #define FRDCMD_SHIFT (8)
106 #define FRDCMD_MASK ((0xff)<<FRDCMD_SHIFT)
107 #define QRDCMDBIT_SHIFT (0)
108 #define QRDCMDBIT_MASK ((0xff)<<QRDCMDBIT_SHIFT)
109 
110 /* 0x34 */
111 #define PULL_UP_DOWN_CONFIG_BASE 0x34
112 #define SPIRUEN_SHIFT (4)
113 #define SPIRUEN_MASK ((0xf)<<SPIRUEN_SHIFT)
114 #define SPIRDEN_SHIFT (0)
115 #define SPIRDEN_MASK ((0xf)<<SPIRDEN_SHIFT)
116 
117 #endif
118 
119