1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef __REG_PSRAM_PHY_V2_H__
5 #define __REG_PSRAM_PHY_V2_H__
6 
7 #include "plat_types.h"
8 
9 struct PSRAM_PHY_T {
10     __IO uint32_t REG_000;
11     __IO uint32_t REG_004;
12     __IO uint32_t REG_008;
13     __IO uint32_t REG_00C;
14     __IO uint32_t REG_010;
15     __IO uint32_t REG_014;
16     __IO uint32_t REG_018;
17     __IO uint32_t REG_01C;
18     __IO uint32_t REG_020;
19     __IO uint32_t REG_024;
20     __IO uint32_t REG_028;
21     __IO uint32_t REG_02C;
22     __IO uint32_t REG_030;
23     __IO uint32_t REG_034;
24     __IO uint32_t REG_038;
25     __IO uint32_t REG_03C;
26     __IO uint32_t REG_040;
27     __IO uint32_t REG_044;
28     __IO uint32_t REG_048;
29     __IO uint32_t REG_04C;
30     __IO uint32_t REG_050;
31     __IO uint32_t REG_054;
32     __IO uint32_t REG_058;
33     __IO uint32_t REG_05C;
34 };
35 
36 // reg_00
37 #define PSRAM_ULP_PHY_CHIP_TYPE                  (1 << 0)
38 #define PSRAM_ULP_PHY_CHIP_BIT                   (1 << 1)
39 #define PSRAM_ULP_PHY_MEMORY_WIDTH(n)            (((n) & 0x3) << 2)
40 #define PSRAM_ULP_PHY_MEMORY_WIDTH_MASK          (0x3 << 2)
41 #define PSRAM_ULP_PHY_MEMORY_WIDTH_SHIFT         (2)
42 #define PSRAM_ULP_PHY_FRE_RATIO(n)               (((n) & 0x3) << 4)
43 #define PSRAM_ULP_PHY_FRE_RATIO_MASK             (0x3 << 4)
44 #define PSRAM_ULP_PHY_FRE_RATIO_SHIFT            (4)
45 
46 // reg_04
47 #define PSRAM_ULP_PHY_CTRL_DELAY(n)              (((n) & 0x3) << 0)
48 #define PSRAM_ULP_PHY_CTRL_DELAY_MASK            (0x3 << 0)
49 #define PSRAM_ULP_PHY_CTRL_DELAY_SHIFT           (0)
50 #define PSRAM_ULP_PHY_RX_DLY_EN                  (1 << 2)
51 #define PSRAM_ULP_PHY_ALIGN_BYPASS               (1 << 3)
52 #define PSRAM_ULP_PHY_PHY_LOOPBACK_EN            (1 << 4)
53 #define PSRAM_ULP_PHY_PHY_DUMMY_CYC_EN           (1 << 5)
54 
55 // reg_08
56 #define PSRAM_ULP_PHY_T_WPST(n)                  (((n) & 0x7) << 0)
57 #define PSRAM_ULP_PHY_T_WPST_MASK                (0x7 << 0)
58 #define PSRAM_ULP_PHY_T_WPST_SHIFT               (0)
59 
60 // reg_0c
61 #define PSRAM_ULP_PHY_RESERVED(n)                (((n) & 0x3F) << 0)
62 #define PSRAM_ULP_PHY_RESERVED_MASK              (0x3F << 0)
63 #define PSRAM_ULP_PHY_RESERVED_SHIFT             (0)
64 
65 // reg_00
66 
67 // reg_10
68 #define PSRAM_ULP_PHY_CMD_CONFLICT_CLR           (1 << 0)
69 
70 // reg_40
71 #define PSRAM_ULP_PHY_PHY_CFG_UPDATE             (1 << 0)
72 
73 // reg_44
74 #define PSRAM_ULP_PHY_CMD_CONFLICT_STS           (1 << 0)
75 #define PSRAM_ULP_PHY_PHY_FSM_STATE(n)           (((n) & 0xF) << 1)
76 #define PSRAM_ULP_PHY_PHY_FSM_STATE_MASK         (0xF << 1)
77 #define PSRAM_ULP_PHY_PHY_FSM_STATE_SHIFT        (1)
78 
79 // reg_48
80 #define PSRAM_ULP_PHY_REG_LDO_PU                 (1 << 0)
81 #define PSRAM_ULP_PHY_REG_LDO_PRECHARGE          (1 << 1)
82 #define PSRAM_ULP_PHY_REG_LDO_IEN1(n)            (((n) & 0xF) << 2)
83 #define PSRAM_ULP_PHY_REG_LDO_IEN1_MASK          (0xF << 2)
84 #define PSRAM_ULP_PHY_REG_LDO_IEN1_SHIFT         (2)
85 #define PSRAM_ULP_PHY_REG_LDO_IEN2(n)            (((n) & 0xF) << 6)
86 #define PSRAM_ULP_PHY_REG_LDO_IEN2_MASK          (0xF << 6)
87 #define PSRAM_ULP_PHY_REG_LDO_IEN2_SHIFT         (6)
88 #define PSRAM_ULP_PHY_REG_LDO_VTUNE(n)           (((n) & 0x7) << 10)
89 #define PSRAM_ULP_PHY_REG_LDO_VTUNE_MASK         (0x7 << 10)
90 #define PSRAM_ULP_PHY_REG_LDO_VTUNE_SHIFT        (10)
91 
92 // reg_4c
93 #define PSRAM_ULP_PHY_REG_PSRAM_PU               (1 << 0)
94 #define PSRAM_ULP_PHY_REG_PSRAM_SWRC(n)          (((n) & 0x3) << 1)
95 #define PSRAM_ULP_PHY_REG_PSRAM_SWRC_MASK        (0x3 << 1)
96 #define PSRAM_ULP_PHY_REG_PSRAM_SWRC_SHIFT       (1)
97 #define PSRAM_ULP_PHY_REG_PSRAM_TXDRV(n)         (((n) & 0x7) << 3)
98 #define PSRAM_ULP_PHY_REG_PSRAM_TXDRV_MASK       (0x7 << 3)
99 #define PSRAM_ULP_PHY_REG_PSRAM_TXDRV_SHIFT      (3)
100 #define PSRAM_ULP_PHY_REG_PSRAM_LOOPBACK_EN      (1 << 6)
101 
102 // reg_50
103 #define PSRAM_ULP_PHY_REG_DLL_PU                 (1 << 0)
104 #define PSRAM_ULP_PHY_REG_DLL_SWRC(n)            (((n) & 0x3) << 1)
105 #define PSRAM_ULP_PHY_REG_DLL_SWRC_MASK          (0x3 << 1)
106 #define PSRAM_ULP_PHY_REG_DLL_SWRC_SHIFT         (1)
107 #define PSRAM_ULP_PHY_REG_DLL_RANGE(n)           (((n) & 0x3) << 3)
108 #define PSRAM_ULP_PHY_REG_DLL_RANGE_MASK         (0x3 << 3)
109 #define PSRAM_ULP_PHY_REG_DLL_RANGE_SHIFT        (3)
110 #define PSRAM_ULP_PHY_REG_DLL_DLY_INI(n)         (((n) & 0xFF) << 5)
111 #define PSRAM_ULP_PHY_REG_DLL_DLY_INI_MASK       (0xFF << 5)
112 #define PSRAM_ULP_PHY_REG_DLL_DLY_INI_SHIFT      (5)
113 #define PSRAM_ULP_PHY_REG_DLL(n)                 (((n) & 0xFF) << 13)
114 #define PSRAM_ULP_PHY_REG_DLL_MASK               (0xFF << 13)
115 #define PSRAM_ULP_PHY_REG_DLL_SHIFT              (13)
116 #define PSRAM_ULP_PHY_REG_BYPASS_DECIMATION      (1 << 16)
117 #define PSRAM_ULP_PHY_REG_DLL_RESETB             (1 << 21)
118 #define PSRAM_ULP_PHY_REG_DLL_CK_RDY             (1 << 22)
119 
120 // reg_54
121 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CEB_DLY(n)    (((n) & 0x1F) << 0)
122 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CEB_DLY_MASK  (0x1F << 0)
123 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CEB_DLY_SHIFT (0)
124 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CLK_DLY(n)    (((n) & 0x1F) << 5)
125 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CLK_DLY_MASK  (0x1F << 5)
126 #define PSRAM_ULP_PHY_REG_PSRAM_TX_CLK_DLY_SHIFT (5)
127 #define PSRAM_ULP_PHY_REG_PSRAM_TX_DQS_DLY(n)    (((n) & 0x1F) << 10)
128 #define PSRAM_ULP_PHY_REG_PSRAM_TX_DQS_DLY_MASK  (0x1F << 10)
129 #define PSRAM_ULP_PHY_REG_PSRAM_TX_DQS_DLY_SHIFT (10)
130 #define PSRAM_ULP_PHY_REG_PSRAM_RX_DQS_DLY(n)    (((n) & 0x1F) << 15)
131 #define PSRAM_ULP_PHY_REG_PSRAM_RX_DQS_DLY_MASK  (0x1F << 15)
132 #define PSRAM_ULP_PHY_REG_PSRAM_RX_DQS_DLY_SHIFT (15)
133 
134 // reg_58
135 #define PSRAM_ULP_PHY_DLL_DLY_IN(n)              (((n) & 0x3F) << 0)
136 #define PSRAM_ULP_PHY_DLL_DLY_IN_MASK            (0x3F << 0)
137 #define PSRAM_ULP_PHY_DLL_DLY_IN_SHIFT           (0)
138 #define PSRAM_ULP_PHY_DLL_LOCK                   (1 << 6)
139 #define PSRAM_ULP_PHY_DLL_ALL_ZERO               (1 << 7)
140 #define PSRAM_ULP_PHY_DLL_ALL_ONE                (1 << 8)
141 
142 #endif
143