1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef __REG_SPI_H__
5 #define __REG_SPI_H__
6 
7 #include "plat_types.h"
8 
9 struct SPI_T
10 {
11     __IO uint32_t SSPCR0;           //0x00000000
12     __IO uint32_t SSPCR1;           //0x00000004
13     __IO uint32_t SSPDR;            //0x00000008
14     __I  uint32_t SSPSR;            //0x0000000C
15     __IO uint32_t SSPCPSR;          //0x00000010
16     __IO uint32_t SSPIMSC;          //0x00000014
17     __I  uint32_t SSPRIS;           //0x00000018
18     __I  uint32_t SSPMIS;           //0x0000001C
19     __O  uint32_t SSPICR;           //0x00000020
20     __IO uint32_t SSPDMACR;         //0x00000024
21          uint32_t reserved[0x18];   //0x00000028
22     __IO uint32_t SSPRXCR;          //0x00000088
23 };
24 
25 #define MAX_SCR                     (0xFF)
26 #define MIN_SCR                     (0)
27 #define MAX_DATA_BITS               (32)
28 #define MIN_DATA_BITS               (4)
29 
30 #define SPI_SSPCR0_DSS(n)           (((n) & 0x1F) << 16)
31 #define SPI_SSPCR0_DSS_MASK         (0x1F << 16)
32 #define SPI_SSPCR0_DSS_SHIFT        (16)
33 #define SPI_SSPCR0_SCR(n)           (((n) & 0xFF) << 8)
34 #define SPI_SSPCR0_SCR_MASK         (0xFF << 8)
35 #define SPI_SSPCR0_SCR_SHIFT        (8)
36 #define SPI_SSPCR0_SPH              (1 << 7)
37 #define SPI_SSPCR0_SPO              (1 << 6)
38 #define SPI_SSPCR0_FRF(n)           (((n) & 3) << 4)
39 #define SPI_SSPCR0_FRF_MASK         (3 << 4)
40 #define SPI_SSPCR0_FRF_SHIFT        (4)
41 
42 #if (CHIP_SPI_VER >= 4)
43 #define SPI_RX_SEL_EN               (1 << 11)
44 #define SPI_SLAVE_ID_SHIFT          (7)
45 #define SPI_SLAVE_ID_MASK           (0xF << SPI_SLAVE_ID_SHIFT)
46 #define SPI_SLAVE_ID(n)             BITFIELD_VAL(SPI_SLAVE_ID, n)
47 #else
48 #define SPI_RX_SEL_EN               (1 << 9)
49 #define SPI_SLAVE_ID_SHIFT          (7)
50 #define SPI_SLAVE_ID_MASK           (3 << SPI_SLAVE_ID_SHIFT)
51 #define SPI_SLAVE_ID(n)             BITFIELD_VAL(SPI_SLAVE_ID, n)
52 #endif
53 #define SPI_LCD_DC_DATA             (1 << 4)
54 #define SPI_SSPCR1_SOD              (1 << 3)
55 #define SPI_SSPCR1_MS               (1 << 2)
56 #define SPI_SSPCR1_SSE              (1 << 1)
57 #define SPI_SSPCR1_LBM              (1 << 0)
58 
59 #define SPI_SSPSR_BSY               (1 << 4)
60 #define SPI_SSPSR_RFF               (1 << 3)
61 #define SPI_SSPSR_RNE               (1 << 2)
62 #define SPI_SSPSR_TNF               (1 << 1)
63 #define SPI_SSPSR_TFE               (1 << 0)
64 
65 #define MAX_CPSDVSR                 (0xFE)
66 #define MIN_CPSDVSR                 (2)
67 
68 #define SPI_SSPCPSR_CPSDVSR(n)      (((n) & 0xFF) << 0)
69 #define SPI_SSPCPSR_CPSDVSR_MASK    (0xFF << 0)
70 #define SPI_SSPCPSR_CPSDVSR_SHIFT   (0)
71 
72 #define SPI_SSPIMSC_TXIM            (1 << 3)
73 #define SPI_SSPIMSC_RXIM            (1 << 2)
74 #define SPI_SSPIMSC_RTIM            (1 << 1)
75 #define SPI_SSPIMSC_RORIM           (1 << 0)
76 
77 #define SPI_SSPRIS_TXRIS            (1 << 3)
78 #define SPI_SSPRIS_RXRIS            (1 << 2)
79 #define SPI_SSPRIS_RTRIS            (1 << 1)
80 #define SPI_SSPRIS_RORRIS           (1 << 0)
81 
82 #define SPI_SSPMIS_TXMIS            (1 << 3)
83 #define SPI_SSPMIS_RXMIS            (1 << 2)
84 #define SPI_SSPMIS_RTMIS            (1 << 1)
85 #define SPI_SSPMIS_RORMIS           (1 << 0)
86 
87 #define SPI_SSPICR_RTIC             (1 << 1)
88 #define SPI_SSPICR_RORIC            (1 << 0)
89 
90 #define SPI_SSPDMACR_TXDMAE         (1 << 1)
91 #define SPI_SSPDMACR_RXDMAE         (1 << 0)
92 
93 #define SPI_SSPRXCR_EN              (1 << 6)
94 #define SPI_SSPRXCR_OEN_POLARITY    (1 << 5)
95 #define SPI_SSPRXCR_RXBITS(n)       (((n) & 0x1F) << 0)
96 #define SPI_SSPRXCR_RXBITS_MASK     (0x1F << 0)
97 #define SPI_SSPRXCR_RXBITS_SHIFT    (0)
98 
99 #endif
100 
101