1 /**************************************************************************//** 2 * @file mpu.h 3 * @brief Defines macros for the MPU registers seting. 4 * 5 * @version V1.00 6 * @date 2017-03-21 7 * 8 * @note 9 * 10 ****************************************************************************** 11 * 12 * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. 13 * 14 * SPDX-License-Identifier: Apache-2.0 15 * 16 * Licensed under the Apache License, Version 2.0 (the License); you may 17 * not use this file except in compliance with the License. 18 * You may obtain a copy of the License at 19 * 20 * http://www.apache.org/licenses/LICENSE-2.0 21 * 22 * Unless required by applicable law or agreed to in writing, software 23 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 24 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 * See the License for the specific language governing permissions and 26 * limitations under the License. 27 * 28 ******************************************************************************/ 29 30 #ifndef _MPU_H_ 31 #define _MPU_H_ 32 33 /** 34 \brief The data structure for a MPU region configuration 35 */ 36 typedef struct { 37 uint32_t region_base; /*!< MPU region base, 32 bytes aligned. */ 38 uint32_t region_size; /*!< MPU region size, 32 bytes aligned. */ 39 uint8_t xn; /*!< eXecute Never attribute. This parameter can be a value of @ref mpu_region_config_xn_define. */ 40 uint8_t ap; /*!< Access permissions. This parameter can be a value of @ref mpu_region_config_ap_define. */ 41 uint8_t sh; /*!< Shareability for Normal memory. This parameter can be a value of @ref mpu_region_config_sh_define. */ 42 uint8_t attr_idx; /*!< memory attribute indirect index. This parameter can be a value of 0~7. */ 43 } mpu_region_config; 44 45 /** @defgroup mpu_region_config_xn_define 46 * @{ 47 * note: eXecute Never attribute(MPU_RBAR[0]): 48 * 0: Allow program execution in this region. 49 * 1: Does not allow program execution in this region. 50 */ 51 #define MPU_EXEC_ALLOW 0 52 #define MPU_EXEC_NEVER 1 53 /** 54 * @} 55 */ 56 57 /** @defgroup mpu_region_config_ap_define 58 * @{ 59 * note: Access permissions (MPU_RBAR[2:1]): 60 * 00: Read/write by privileged code only. 61 * 01: Read/write by any privilege level. 62 * 10: Read only by privileged code only. 63 * 11: Read only by any privilege level. 64 */ 65 #define MPU_PRIV_RW (0 << 1) 66 #define MPU_UN_PRIV_RW (1 << 1) 67 #define MPU_PRIV_R (2 << 1) 68 #define MPU_PRIV_W (3 << 1) 69 /** 70 * @} 71 */ 72 73 /** @defgroup mpu_region_config_sh_define 74 * @{ 75 * note: Shareability for Normal memory(MPU_RBAR[4:3]): 76 * 00: Non-shareable. 77 * 01: Reserved. 78 * 10: Outer shareable. 79 * 11: Inner shareable. 80 */ 81 #define MPU_NON_SHAREABLE (0 << 3) 82 #define MPU_OUT_SHAREABLE (2 << 3) 83 #define MPU_INR_SHAREABLE (3 << 3) 84 /** 85 * @} 86 */ 87 #if defined (ARM_CORE_CM4) 88 #define MPU_MAX_REGION 8 89 #else 90 #define MPU_MAX_REGION 4 91 #endif 92 /** @defgroup mpu_region_memory_attribute_define 93 * @{ 94 * note: Outer, bits [7:4]: 95 * 0b0000 Device memory. 96 * 0b00RW Normal memory, Outer write-through transient (RW!='00'). 97 * 0b0100 Normal memory, Outer non-cacheable. 98 * 0b01RW Normal memory, Outer write-back transient (RW!='00'). 99 * 0b10RW Normal memory, Outer write-through non-transient. 100 * 0b11RW Normal memory, Outer write-back non-transient. 101 * note: The transient attribute indicates that the benefit of caching is for a relatively short period, 102 * and that therefore it might be better to restrict allocation, to avoid possibly casting-out other, 103 * less transient, entries. 104 * note: Inner, bits [3:0], when Outer != '0000' 105 * 0b00RW Normal memory, Inner write-through transient (RW!='00'). 106 * 0b0100 Normal memory, Inner non-cacheable. 107 * 0b01RW Normal memory, Inner write-back transient (RW!='00'). 108 * 0b10RW Normal memory, Inner write-through non-transient. 109 * 0b11RW Normal memory, Inner write-back non-transient 110 */ 111 // define memory attribute of Normal memory with write-through transient, write allocation 112 #define NORMAL_WT_T_WA (0x01) 113 114 // define memory attribute of Normal memory with write-through transient, read allocation 115 #define NORMAL_WT_T_RA (0x02) 116 117 // define memory attribute of Normal memory with write-through transient, read & write allocation 118 #define NORMAL_WT_T_RWA (0x03) 119 120 // define memory attribute of Normal memory with non-cacheable 121 #define NORMAL_NC (0x04) 122 123 // define memory attribute of Normal memory with write-back transient, write allocation 124 #define NORMAL_WB_T_WA (0x05) 125 126 // define memory attribute of Normal memory with write-back transient, read allocation 127 #define NORMAL_WB_T_RA (0x06) 128 129 // define memory attribute of Normal memory with write-back transient, read and write allocation 130 #define NORMAL_WB_T_RWA (0x07) 131 132 // define memory attribute of Normal memory with write-through non-transient, no allocation 133 #define NORMAL_WT_NT (0x08) 134 135 // define memory attribute of Normal memory with write-through non-transient, write allocation 136 #define NORMAL_WT_NT_WA (0x09) 137 138 // define memory attribute of Normal memory with write-through non-transient, read allocation 139 #define NORMAL_WT_NT_RA (0x0A) 140 141 // define memory attribute of Normal memory with write-through non-transient, read and write allocation 142 #define NORMAL_WT_NT_RWA (0x0B) 143 144 // define memory attribute of Normal memory with write-back non-transient, no allocation 145 #define NORMAL_WB_NT (0x0C) 146 147 // define memory attribute of Normal memory with write-back non-transient, write allocation 148 #define NORMAL_WB_NT_WA (0x0D) 149 150 // define memory attribute of Normal memory with write-back non-transient, read allocation 151 #define NORMAL_WB_NT_RA (0x0E) 152 153 // define memory attribute of Normal memory with write-back non-transient, read and write allocation 154 #define NORMAL_WB_NT_RWA (0x0F) 155 /** 156 * @} 157 */ 158 159 /** @defgroup mpu_region_device_attribute_define 160 * @{ 161 * note: Device, bits [3:2], when Outer == '0000': 162 * 0b00 Device-nGnRnE. 163 * 0b01 Device-nGnRE. 164 * 0b10 Device-nGRE. 165 * 0b11 Device-GRE. 166 */ 167 // define memory attribute of Device memory with non-gathering, non-reording, non-Early Write Acknowledge 168 #define DEVICE_NG_NR_NE ((0<<4)|(0<<2)) 169 170 // define memory attribute of Device memory with non-gathering, non-reording, Early Write Acknowledge 171 #define DEVICE_NG_NR_E ((0<<4)|(1<<2)) 172 173 // define memory attribute of Device memory with non-gathering, reording, Early Write Acknowledge 174 #define DEVICE_NG_R_E ((0<<4)|(2<<2)) 175 176 // define memory attribute of Device memory with gathering, reording, Early Write Acknowledge 177 #define DEVICE_G_R_E ((0<<4)|(3<<2)) 178 /** 179 * @} 180 */ 181 182 void mpu_init (void); 183 void mpu_set_mem_attr(uint8_t attr_idx, uint8_t mem_attr); 184 void mpu_region_cfg(uint8_t region_num, mpu_region_config *pmpu_cfg); 185 void mpu_enable(void); 186 void mpu_disable(void); 187 void mpu_entry_free(u32 entry_index); 188 char mpu_entry_alloc(void); 189 190 #endif //_MPU_H_ 191 192