1 2 /* 3 * Arm SCP/MCP Software 4 * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 * 8 * Description: 9 * CMN600 CCIX Configuration Interface 10 */ 11 12 #ifndef INTERNAL_CMN600_CCIX_H 13 #define INTERNAL_CMN600_CCIX_H 14 15 #include <internal/cmn600_ctx.h> 16 17 #include <fwk_module_idx.h> 18 19 #include <stdbool.h> 20 #include <stdint.h> 21 22 /* 23 * CMN600 CCIX Setup Function 24 */ 25 int ccix_setup(struct cmn600_ctx *ctx, void *remote_config); 26 27 /* 28 * CMN600 CCIX Exchange Protocol Credit Function 29 */ 30 int ccix_exchange_protocol_credit(struct cmn600_ctx *ctx, uint8_t link_id); 31 32 /* 33 * CMN600 CCIX Enter system Coherency Function 34 */ 35 int ccix_enter_system_coherency(struct cmn600_ctx *ctx, uint8_t link_id); 36 37 /* 38 * CMN600 CCIX Enter DVM domain Function 39 */ 40 int ccix_enter_dvm_domain(struct cmn600_ctx *ctx, uint8_t link_id); 41 42 /* 43 * CMN600 CCIX get Capabilities Function 44 */ 45 void ccix_capabilities_get(struct cmn600_ctx *ctx); 46 47 /* 48 * CCIX Gateway (CXG) protocol link control & status registers 49 */ 50 struct cxg_link_regs { 51 FWK_RW uint64_t CXG_PRTCL_LINK_CTRL; 52 FWK_R uint64_t CXG_PRTCL_LINK_STATUS; 53 }; 54 55 /* 56 * CCIX Gateway (CXG) Home Agent (HA) registers 57 */ 58 struct cmn600_cxg_ha_reg { 59 FWK_R uint64_t CXG_HA_NODE_INFO; 60 FWK_RW uint64_t CXG_HA_ID; 61 uint8_t RESERVED0[0x80-0x10]; 62 FWK_R uint64_t CXG_HA_CHILD_INFO; 63 uint8_t RESERVED1[0x900-0x88]; 64 FWK_R uint64_t CXG_HA_UNIT_INFO; 65 uint8_t RESERVED2[0x980-0x908]; 66 FWK_RW uint64_t CXG_HA_SEC_REG_GRP_OVERRIDE; 67 uint8_t RESERVED3[0xA08-0x988]; 68 FWK_RW uint64_t CXG_HA_AUX_CTRL; 69 uint8_t RESERVED4[0xC00-0xA10]; 70 FWK_RW uint64_t CXG_HA_RNF_RAID_TO_LDID_REG[8]; 71 FWK_RW uint64_t CXG_HA_AGENTID_TO_LINKID_REG[8]; 72 uint8_t RESERVED5[0xD00-0xC80]; 73 FWK_RW uint64_t CXG_HA_AGENTID_TO_LINKID_VAL; 74 FWK_RW uint64_t CXG_HA_RNF_RAID_TO_LDID_VAL; 75 uint8_t RESERVED6[0x1000-0xD10]; 76 struct cxg_link_regs LINK_REGS[3]; 77 uint8_t RESERVED7[0x2000-0x1030]; 78 FWK_RW uint64_t CXG_HA_PMU_EVENT_SEL; 79 }; 80 81 /* 82 * CCIX Gateway (CXG) Requesting Agent (RA) registers 83 */ 84 struct cmn600_cxg_ra_reg { 85 FWK_R uint64_t CXG_RA_NODE_INFO; 86 uint8_t RESERVED0[0x80-0x8]; 87 FWK_R uint64_t CXG_RA_CHILD_INFO; 88 uint8_t RESERVED1[0x900-0x88]; 89 FWK_R uint64_t CXG_RA_UNIT_INFO; 90 uint8_t RESERVED2[0x980-0x908]; 91 FWK_RW uint64_t CXG_RA_SEC_REG_GRP_OVERRIDE; 92 uint8_t RESERVED3[0xA00-0x988]; 93 FWK_RW uint64_t CXG_RA_CFG_CTRL; 94 FWK_RW uint64_t CXG_RA_AUX_CTRL; 95 uint8_t RESERVED4[0xDA8-0xA10]; 96 FWK_RW uint64_t CXG_RA_SAM_ADDR_REGION_REG[8]; 97 uint8_t RESERVED5[0xE00-0xDE8]; 98 FWK_RW uint64_t CXG_RA_SAM_MEM_REGION_LIMIT_REG[8]; 99 uint8_t RESERVED6[0xE60-0xE40]; 100 FWK_RW uint64_t CXG_RA_AGENTID_TO_LINKID_REG[8]; 101 FWK_RW uint64_t CXG_RA_RNF_LDID_TO_RAID_REG[8]; 102 FWK_RW uint64_t CXG_RA_RNI_LDID_TO_RAID_REG[4]; 103 FWK_RW uint64_t CXG_RA_RND_LDID_TO_RAID_REG[4]; 104 FWK_RW uint64_t CXG_RA_AGENTID_TO_LINKID_VAL; 105 FWK_RW uint64_t CXG_RA_RNF_LDID_TO_RAID_VAL; 106 FWK_RW uint64_t CXG_RA_RNI_LDID_TO_RAID_VAL; 107 FWK_RW uint64_t CXG_RA_RND_LDID_TO_RAID_VAL; 108 uint8_t RESERVED7[0x1000-0xF40]; 109 struct cxg_link_regs LINK_REGS[3]; 110 uint8_t RESERVED8[0x2000-0x1030]; 111 FWK_RW uint64_t CXG_RA_PMU_EVENT_SEL; 112 }; 113 114 /* 115 * CCIX Gateway (CXG) Link Agent (LA) registers 116 */ 117 struct cmn600_cxla_reg { 118 FWK_R uint64_t CXLA_NODE_INFO; 119 uint8_t RESERVED0[0x80-0x8]; 120 FWK_R uint64_t CXLA_CHILD_INFO; 121 uint8_t RESERVED1[0x900-0x88]; 122 FWK_R uint64_t CXLA_UNIT_INFO; 123 uint8_t RESERVED2[0x980-0x908]; 124 FWK_RW uint64_t CXLA_SEC_REG_GRP_OVERRIDE; 125 uint8_t RESERVED3[0xA08-0x988]; 126 FWK_RW uint64_t CXLA_AUX_CTRL; 127 uint8_t RESERVED4[0xC00-0xA10]; 128 FWK_R uint64_t CXLA_CCIX_PROP_CAPABILITIES; 129 FWK_RW uint64_t CXLA_CCIX_PROP_CONFIGURED; 130 FWK_R uint64_t CXLA_TX_CXS_ATTR_CAPABILITIES; 131 FWK_R uint64_t CXLA_RX_CXS_ATTR_CAPABILITIES; 132 uint8_t RESERVED5[0xC30-0xC20]; 133 FWK_RW uint64_t CXLA_AGENTID_TO_LINKID_REG[8]; 134 FWK_RW uint64_t CXLA_AGENTID_TO_LINKID_VAL; 135 FWK_RW uint64_t CXLA_LINKID_TO_PCIE_BUS_NUM; 136 FWK_RW uint64_t CXLA_PCIE_HDR_FIELDS; 137 }; 138 139 140 141 /* 142 * CCIX Definitions 143 */ 144 145 /* 146 * CCIX Link UP stages 147 */ 148 enum cxg_link_up_wait_cond { 149 CXG_LINK_CTRL_EN_BIT_SET, 150 CXG_LINK_CTRL_UP_BIT_CLR, 151 CXG_LINK_STATUS_DWN_BIT_SET, 152 CXG_LINK_STATUS_DWN_BIT_CLR, 153 CXG_LINK_STATUS_ACK_BIT_SET, 154 CXG_LINK_STATUS_ACK_BIT_CLR, 155 CXG_LINK_STATUS_HA_DVMDOMAIN_ACK_BIT_SET, 156 CXG_LINK_STATUS_RA_DVMDOMAIN_ACK_BIT_SET, 157 CXG_LINK_UP_SEQ_COUNT, 158 }; 159 160 /* 161 * Structure defining data to be passed to timer API 162 */ 163 struct cxg_wait_condition_data { 164 struct cmn600_ctx *ctx; 165 uint8_t link_id; 166 enum cxg_link_up_wait_cond cond; 167 }; 168 169 /* CCIX Gateway (CXG) Request Agent (RA) defines */ 170 171 #define CXG_RA_SAM_HA_TGT_ID_SHIFT_VAL 52 172 #define CXG_RA_RNF_LDID_TO_RAID_REG_OFFSET 0xEA0 173 #define CXG_RA_RNI_LDID_TO_RAID_REG_OFFSET 0xEE0 174 #define CXG_RA_RND_LDID_TO_RAID_REG_OFFSET 0xF00 175 #define CXG_RA_RNF_RAID_VALID_REG_OFFSET 0xF28 176 #define CXG_RA_RNI_RAID_VALID_REG_OFFSET 0xF30 177 #define CXG_RA_RND_RAID_VALID_REG_OFFSET 0xF38 178 #define CXG_RA_AGENTID_TO_LINKID_OFFSET 0xE60 179 #define CXG_RA_AGENTID_TO_LINKID_VAL_OFFSET 0xF20 180 #define CXG_RA_REQUEST_TRACKER_DEPTH_MASK UINT64_C(0x0000000001FF0000) 181 #define CXG_RA_REQUEST_TRACKER_DEPTH_VAL 16 182 #define CXG_RA_UNIT_INFO_SMP_MODE_RO_MASK (UINT64_C(1) << 61) 183 #define CXG_RA_AUX_CTRL_SMP_MODE_RW_SHIFT_VAL (16) 184 185 /* CCIX Gateway (CXG) Home Agent (HA) defines */ 186 187 #define CXG_HA_AGENTID_TO_LINKID_OFFSET 0xC40 188 #define CXG_HA_AGENTID_TO_LINKID_VAL_OFFSET 0xD00 189 #define CXG_HA_RAID_TO_LDID_OFFSET (0xC00) 190 #define CXG_HA_RAID_TO_LDID_VALID_OFFSET (0xD08) 191 #define CXG_HA_RAID_TO_LDID_RNF_MASK (0x80) 192 #define CXG_HA_LDID_TO_RAID_OFFSET 0xC00 193 #define CXG_HA_SNOOP_TRACKER_DEPTH_MASK UINT64_C(0x00001FF000000000) 194 #define CXG_HA_SNOOP_TRACKER_DEPTH_VAL 36 195 #define CXG_HA_WDB_DEPTH_MASK UINT64_C(0x0000000007FC0000) 196 #define CXG_HA_WDB_DEPTH_VAL 18 197 #define CXG_HA_UNIT_INFO_SMP_MODE_RO_MASK (UINT64_C(1) << 63) 198 #define CXG_HA_AUX_CTRL_SMP_MODE_RW_SHIFT_VAL (16) 199 200 /* CCIX Gateway (CXG) Link Agent (LA) defines */ 201 202 #define CXLA_AGENTID_TO_LINKID_OFFSET 0xC30 203 #define CXLA_AGENTID_TO_LINKID_VAL_OFFSET 0xC70 204 205 #define CXLA_CCIX_PROP_MSG_PACK_SHIFT_MASK UINT64_C(0x0000000000000400) 206 #define CXLA_CCIX_PROP_MSG_PACK_SHIFT_VAL 10 207 208 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_MASK UINT64_C(0x0000000000000380) 209 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_SHIFT_VAL 7 210 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_128 0 211 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_256 1 212 #define CXLA_CCIX_PROP_MAX_PACK_SIZE_512 2 213 214 #define CXLA_PCIE_HDR_TRAFFIC_CLASS_MASK UINT64_C(0x0000000000007000) 215 #define CXLA_PCIE_HDR_VENDOR_ID_MASK UINT64_C(0x0000FFFF00000000) 216 217 #define CXLA_PCIE_HDR_TRAFFIC_CLASS_SHIFT_VAL 12 218 #define CXLA_PCIE_HDR_VENDOR_ID_SHIFT_VAL 32 219 220 #define CXLA_AUX_CTRL_SMP_MODE_SHIFT_VAL (47) 221 222 /* CCIX Gateway (CXG) link control & status defines */ 223 224 #define CXG_LINK_CTRL_EN_MASK UINT64_C(0x0000000000000001) 225 #define CXG_LINK_CTRL_REQ_MASK UINT64_C(0x0000000000000002) 226 #define CXG_LINK_CTRL_UP_MASK UINT64_C(0x0000000000000004) 227 #define CXG_LINK_CTRL_DVMDOMAIN_REQ_MASK UINT64_C(0x0000000000000008) 228 #define CXG_LINK_STATUS_ACK_MASK UINT64_C(0x0000000000000001) 229 #define CXG_LINK_STATUS_DOWN_MASK UINT64_C(0x0000000000000002) 230 #define CXG_LINK_STATUS_DVMDOMAIN_ACK_MASK UINT64_C(0x0000000000000004) 231 #define CXG_PRTCL_LINK_CTRL_TIMEOUT UINT32_C(100) 232 #define CXG_PRTCL_LINK_DVMDOMAIN_TIMEOUT UINT32_C(100) 233 234 #define RAID_RNF_BIT_SHIFT_VAL 7 235 #define HNF_RN_PHYS_NODE_ID_SHIFT_VAL 16 236 #define HNF_RN_PHYS_RN_ID_VALID_SHIFT_VAL 31 237 #define HNF_RN_PHYS_RN_LOCAL_REMOTE_SHIFT_VAL 16 238 #define NUM_BITS_RESERVED_FOR_RAID 8 239 #define NUM_BITS_RESERVED_FOR_LINK_ID 8 240 #define NUM_BITS_RESERVED_FOR_LDID 8 241 #define NUM_BITS_RESERVED_FOR_PHYS_ID 32 242 #define HNF_RN_PHYS_ID_OFFSET 0xD28 243 #define LOCAL_CCIX_NODE 0 244 #define REMOTE_CCIX_NODE 1 245 #define SAM_ADDR_HOME_AGENT_ID_SHIFT (52) 246 #define SAM_ADDR_REG_VALID_MASK UINT64_C(0x8000000000000000) 247 #define PCIE_OPT_HDR_MASK (0x1ULL << 6) 248 #define CTL_NUM_SNPCRDS_MASK (0xF << 4) 249 #define CCIX_VENDER_ID (0x1E2C) 250 251 #endif /* INTERNAL_CMN600_CCIX_H */ 252