1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * Definitions and utility functions for the I2C controller module. 9 */ 10 11 #ifndef DW_APB_I2C_H 12 #define DW_APB_I2C_H 13 14 #include <fwk_macros.h> 15 16 #include <stdint.h> 17 18 #define I2C_TRANSMIT_BUFFER_LENGTH 16 19 #define I2C_RECEIVE_BUFFER_LENGTH 16 20 #define I2C_TIMEOUT_US 250 21 22 /* 23 * I2C controller register definitions 24 */ 25 struct dw_apb_i2c_reg { 26 uint8_t RESERVED0[0x04 - 0x00]; 27 FWK_RW uint32_t IC_TAR; 28 uint8_t RESERVED1[0x10 - 0x08]; 29 FWK_RW uint32_t IC_DATA_CMD; 30 uint8_t RESERVED2[0x2C - 0x14]; 31 FWK_R uint32_t IC_INTR_STAT; 32 FWK_RW uint32_t IC_INTR_MASK; 33 uint8_t RESERVED3[0x54 - 0x34]; 34 FWK_R uint32_t IC_CLR_TX_ABRT; 35 uint8_t RESERVED4[0x60 - 0x58]; 36 FWK_R uint32_t IC_CLR_STOP_DET; 37 uint8_t RESERVED5[0x6C - 0x64]; 38 FWK_RW uint32_t IC_ENABLE; 39 FWK_R uint32_t IC_STATUS; 40 uint8_t RESERVED6[0x9C - 0x74]; 41 FWK_R uint32_t IC_ENABLE_STATUS; 42 uint8_t RESERVED7[0x100 - 0xA0]; 43 }; 44 45 #define IC_TAR_ADDRESS UINT32_C(0x000003FF) 46 47 #define IC_ENABLE_STATUS_MASK UINT32_C(0x00000001) 48 #define IC_ENABLE_STATUS_DISABLED 0x0 49 #define IC_ENABLE_STATUS_ENABLED 0x1 50 51 #define IC_STATUS_MST_ACTIVITY_MASK UINT32_C(0x00000020) 52 #define IC_STATUS_TFNF_MASK UINT32_C(0x00000002) 53 54 #define IC_DATA_CMD_CMD_MASK UINT32_C(0x00000100) 55 #define IC_DATA_CMD_DATA_MASK UINT32_C(0x000000FF) 56 57 /* 58 * Command modes for IC_DATA_CMD 59 * Note: Bit [8] will be cleared when a new byte is written into the IC_DATA_CMD 60 * register, setting write mode automatically. 61 */ 62 #define IC_DATA_CMD_READ 0x100 63 64 /* IRQ Masks */ 65 #define IC_INTR_TX_ABRT_POS 6 66 #define IC_INTR_TX_ABRT_MASK (UINT32_C(1) << IC_INTR_TX_ABRT_POS) 67 68 #define IC_INTR_STOP_DET_POS 9 69 #define IC_INTR_STOP_DET_MASK (UINT32_C(1) << IC_INTR_STOP_DET_POS) 70 71 #endif /* DW_APB_I2C_H */ 72