1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef GTIMER_REG_H 9 #define GTIMER_REG_H 10 11 #include <fwk_macros.h> 12 13 #include <stdint.h> 14 15 /*! 16 * \brief Counter registers (CNTCONTROL) 17 */ 18 struct cntcontrol_reg { 19 FWK_RW uint32_t CR; 20 FWK_R uint32_t SR; 21 FWK_RW uint32_t CVL; 22 FWK_RW uint32_t CVH; 23 uint32_t RESERVED0[4]; 24 FWK_RW uint32_t FID0; 25 uint8_t RESERVED1[0xC0 - 0x24]; 26 FWK_RW uint32_t SCR; /* CSS: Synchronization Control Register */ 27 FWK_R uint32_t SVL; /* CSS: Synchronized Counter Lower Value Register */ 28 FWK_R uint32_t SVU; /* CSS: Synchronized Counter Upper Value Register */ 29 uint8_t RESERVED2[0xFD0 - 0xCC]; 30 FWK_R uint32_t PID[11]; 31 }; 32 33 #define CNTCONTROL_CR_EN UINT32_C(0x00000001) 34 #define CNTCONTROL_CR_HDBG UINT32_C(0x00000002) 35 #define CNTCONTROL_CR_FCREQ UINT32_C(0x00000100) 36 37 #define CNTCONTROL_SCR_ENSYNC UINT32_C(0x00000001) 38 #define CNTCONTROL_SCR_ENSYNC_DIRECT UINT32_C(0x00000000) 39 #define CNTCONTROL_SCR_ENSYNC_DELAY UINT32_C(0x00000001) 40 41 /*! 42 * \brief Counter registers (CNTCTL) 43 */ 44 struct cntctl_reg { 45 FWK_RW uint32_t FRQ; 46 FWK_RW uint32_t NSAR; 47 FWK_R uint32_t TTIDR; 48 uint8_t RESERVED0[0x40 - 0x0C]; 49 FWK_RW uint32_t ACR; 50 uint8_t RESERVED1[0xFD0 - 0x44]; 51 FWK_R uint32_t PID[11]; 52 }; 53 54 #define CNTCTL_ACR UINT32_C(0x0000003f) 55 #define CNTCTL_ACR_RPCT UINT32_C(0x00000001) 56 #define CNTCTL_ACR_RVCT UINT32_C(0x00000002) 57 #define CNTCTL_ACR_RFRQ UINT32_C(0x00000004) 58 #define CNTCTL_ACR_RVOFF UINT32_C(0x00000008) 59 #define CNTCTL_ACR_RWVT UINT32_C(0x00000010) 60 #define CNTCTL_ACR_RWPT UINT32_C(0x00000020) 61 62 /*! 63 * \brief Counter registers (CNTBASE) 64 */ 65 struct cntbase_reg { 66 FWK_R uint32_t PCTL; 67 FWK_R uint32_t PCTH; 68 FWK_R uint32_t VCTL; 69 FWK_R uint32_t VCTH; 70 FWK_R uint32_t FRQ; 71 FWK_RW uint32_t PL0ACR; 72 FWK_R uint32_t OFFL; 73 FWK_R uint32_t OFFH; 74 FWK_RW uint32_t P_CVALL; 75 FWK_RW uint32_t P_CVALH; 76 FWK_RW uint32_t P_TVAL; 77 FWK_RW uint32_t P_CTL; 78 FWK_RW uint32_t V_CVALL; 79 FWK_RW uint32_t V_CVALH; 80 FWK_RW uint32_t V_TVAL; 81 FWK_RW uint32_t V_CTL; 82 uint8_t RESERVED0[0xFD0 - 0x40]; 83 FWK_R uint32_t PID[11]; 84 }; 85 86 #define CNTBASE_P_CTL UINT32_C(0x00000007) 87 #define CNTBASE_P_CTL_ENABLE UINT32_C(0x00000001) 88 #define CNTBASE_P_CTL_IMASK UINT32_C(0x00000002) 89 #define CNTBASE_P_CTL_ISTATUS UINT32_C(0x00000004) 90 91 #endif /* GTIMER_REG_H */ 92