1\ingroup GroupModules Modules
2\defgroup GroupMPMM Max Power Mitigation Mechanism (MPMM)
3
4Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
5
6MPMM Module Description
7=======================
8
9# Overview {#module_mpmm_overview}
10
11This module provides the MPMM (Maximum Power Mitigation Mechanism) algorithm.
12This mechanism detects and limits high activity events to assist in processor
13power domain dynamic power budgeting and limit the triggering of whole-rail
14responses to overcurrent conditions.
15
16The algorithm will monitor MPMM threshold counters and controls the performance
17limits and thresholds. Metrics are provided for each domain so the SCP can use
18it to budget the power by limiting the number of cores that can execute higher
19activity workloads and switching to a different DVFS operating point.
20
21# MPMM design {#module_mpmm_design}
22
23Each set of cores supporting MPMM and supplied by a single rail is represented
24by a domain. A core inside the domain is handled as sub-element. For each core,
25there is a set of MPMM counters and threshold registers. The algorithm is split
26into two parts. The first part evaluates each core state individually. The
27second part evaluates the performance requests for all cores within one domain.
28The correct threshold settings for each core are then applied and the new
29performance limits are requested.
30
31# MPMM configuration {#module_mpmm_configuration}
32
33To use this module the platform code needs to provide the following
34configuration options:
35
36## Performance Constraint Table (PCT):
37This table lists the thresholds map and the performance limits according to the
38number of cores online for each domain.
39
40The number of cores online entry represents the number of cores in the power-on
41state. The maximum number of cores supported in a domain is 8.
42The entries should be provided in a numerically descending order as shown in the
43example table below.
44
45Number of performance limits is the number of threshold - performance limit
46tuples. There should be one entry for each number of cores online.
47
48The Threshold map is a 32-bit value. Each 4-bits represents the threshold state
49of one core. The threshold map is arranged in a numerically descending order and
50not in the order of the core indexes. The threshold map entries should be
51provided in a numerically descending order at every performance limit change
52step. The number of table entries and the exact values should be populated
53according to the hardware implementation.
54
55Performance limit is the domain performance level limit for each cores states
56described by the threshold bitmap.
57
58This table is an example for a 4 cores in a domain and 3 levels of supported
59MPMM thresholds:
60
61| Number of cores online | Number of OPP | Threshold bitmap |   perf limit   |
62|          :---:         |     :----:    |      :----:      |      :---:     |
63|            4           |       3       |      0x2222      |      2000      |
64|                        |               |      0x2211      |      2500      |
65|                        |               |      0x2110      |      3000      |
66|            3           |       2       |       0x222      |      2500      |
67|                        |               |       0x110      |      3000      |
68|            2           |       1       |        0x22      |      3000      |
69
70
71## Base Throttling Count (BTC):
72BTC represents the maximum steady state MPMM throttling count which a platform
73wants to maintain for each core. The algorithm will try to find threshold
74combinations which keeps the MPMM throttling around this level while trying to
75maximize performance.
76It is a configuration parameter for the platform to tune. If all the MPMM
77counters differences are below the BTC the highest threshold is selected. If one
78or more of the MPMM counters differences are above the BTC the next threshold
79whose counter delta is just above the BTC is selected.
80