1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef MOD_MPMM_H
9 #define MOD_MPMM_H
10 
11 #include <fwk_id.h>
12 
13 #include <stddef.h>
14 #include <stdint.h>
15 
16 /*!
17  * \ingroup GroupModules
18  *  \defgroup GroupMPMM Max Power Mitigation Mechanism (MPMM)
19  * \{
20  */
21 
22 /*! Maximum number of thresholds allowed. */
23 #define MPMM_MAX_THRESHOLD_COUNT 8
24 
25 /*! How many bits for each threshold in the PCT. */
26 #define MPMM_THRESHOLD_MAP_NUM_OF_BITS 4
27 
28 /*! Maximum number of supported cores per domain. */
29 #define MPMM_MAX_NUM_CORES_IN_DOMAIN 8
30 
31 /*!
32  * \brief MPMM threshold to maximum performance mapping.
33  */
34 struct mod_mpmm_threshold_perf {
35     /*!
36      * \brief Cores bitmap representing thresholds states.
37      *
38      * \details The threshold bitmap is a description of the threshold status of
39      *      each online core. Each core is assigned 4-bits and a maximum of 8
40      *      cores per domain is allowed. The bitmap must be arranged in
41      *      numerically descending order. The lowest threshold is the least
42      *      significant 4-bits. The next lowest threshold should be placed in
43      *      the next lowest 4-bits. There is no relation between the core index
44      *      number and the position of the threshold in this bitmap.
45      *
46      *      Example for a system with four cores:
47      *
48      *      4-cores online                  3-cores online
49      *      +------+------+                 +------+------+
50      *      | Core | thrd |                 | Core | thrd |
51      *      +------+------+                 +------+------+
52      *      |   0  |   2  |                 |   0  |   2  |
53      *      |   1  |   3  |                 |   1  |   3  |
54      *      |   2  |   0  |                 |   -  |   -  |
55      *      |   3  |   2  |                 |   3  |   2  |
56      *      +------+------+                 +------+------+
57      *      bitmap = 0x3220                 bitmap = 0x0322
58      *      (Note the numerically descending order arrangement.)
59      */
60     uint32_t threshold_bitmap;
61 
62     /*!
63      * \brief Maximum allowed performance level for the thresholds states.
64      *
65      * \details The performance limit required when the cores are in this
66      *      particular threshold_bitmap state.
67      */
68     uint32_t perf_limit;
69 };
70 
71 /*!
72  * \brief Perf Constraint Lookup Table (PCT) entry.
73  *
74  * \details The table entries should be provided in numerically descending
75  *          order with respect to the number of online cores. The first
76  *          entry must represent the maximum number of cores.
77  */
78 struct mod_mpmm_pct_table {
79     /*! Number of cores online. */
80     uint32_t cores_online;
81 
82     /*!
83      * \brief Default maximum performance level for the number of cores online
84      *      given by cores_online.
85      *
86      * \details This performance limit will be selected if no suitable value is
87      *      found in the threshold_perf table.
88      */
89     uint32_t default_perf_limit;
90 
91     /*! Number of performance levels entries in the threshold_perf table. */
92     uint32_t num_perf_limits;
93 
94     /*!
95      * \brief Array of threshold_map and performance level pairs.
96      *
97      * \details The threshold_map entries are provided in numerically descending
98      *      order at every performance level.
99      */
100     struct mod_mpmm_threshold_perf threshold_perf[MPMM_MAX_NUM_CORES_IN_DOMAIN];
101 };
102 
103 /*!
104  * \brief MPMM sub-element configuration.
105  *
106  * \details The configuration data of each core.
107  */
108 struct mod_mpmm_core_config {
109     /*! Identifier of the power domain associated with each core. */
110     fwk_id_t pd_id;
111 
112     /*! Base address of the MPMM registers */
113     uintptr_t mpmm_reg_base;
114 
115     /*! Base address of the AMU Auxiliry registers */
116     uintptr_t amu_aux_reg_base;
117 
118     /*! Core initial power state when the platfrom starts is ON. */
119     bool core_starts_online;
120 };
121 
122 /*!
123  * \brief MPMM domain configuration.
124  *
125  */
126 struct mod_mpmm_domain_config {
127     /*! List of core configurations. */
128     struct mod_mpmm_core_config const *core_config;
129 
130     /*! Perf Constraint Table (PCT) for each domain. */
131     struct mod_mpmm_pct_table *pct;
132 
133     /*! Size of the Perf Constraint Table in bytes. */
134     size_t pct_size;
135 
136     /*! Base throttling Count */
137     uint32_t btc;
138 
139     /*! Number of threshold counters */
140     uint32_t num_threshold_counters;
141 
142     /*! Identifier of the performance domain associated with mpmm domain. */
143     fwk_id_t perf_id;
144 };
145 
146 /*!
147  * \}
148  */
149 
150 #endif /* MOD_MPMM_H */
151