1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  *
7  * Description:
8  *     PCIe Integration Control register intialization module for Neoverse
9  *     reference design platforms.
10  */
11 
12 #ifndef MOD_PCIE_INTEG_CTRL_H
13 #define MOD_PCIE_INTEG_CTRL_H
14 
15 #include <fwk_id.h>
16 
17 #include <stddef.h>
18 #include <stdint.h>
19 
20 /*!
21  * \addtogroup GroupModules Modules
22  * \{
23  */
24 
25 /*!
26  * \ingroup GroupModules Modules
27  * \defgroup GroupModulePCIeIntegCtrl PCIe integ ctrl
28  *
29  * \brief PCIe integration control module.
30  *
31  * \details This module implements PCIe integration control register
32  *    initialization.
33  * \{
34  */
35 
36 /*!
37  * \brief ECAM1, 32-bit and 64-bit MMIO space start and end address
38  */
39 struct pcie_ecam_mmio_mmap {
40     /*! Valid flag to indicate if the mapping is valid to program */
41     bool valid;
42 
43     /*! Allow non-secure access
44      *
45      * By default only secure accesses are allowed. Set this to true to allow
46      * non-secure access as well.
47      */
48     bool allow_ns_access;
49 
50     /*! ECAM1 start address */
51     uint64_t ecam1_start_addr;
52 
53     /*! ECAM1 end address */
54     uint64_t ecam1_end_addr;
55 
56     /*! 32-bit MMIO space start address */
57     uint64_t mmiol_start_addr;
58 
59     /*! 32-bit MMIO space end address */
60     uint64_t mmiol_end_addr;
61 
62     /*! 64-bit MMIO space start address */
63     uint64_t mmioh_start_addr;
64 
65     /*! 64-bit MMIO space end address */
66     uint64_t mmioh_end_addr;
67 };
68 
69 /*!
70  * \brief PCIe Integration control registers configuration data which contains
71  * mapping of x4_0, x4_1, x8 and x16.
72  */
73 struct mod_pcie_integ_ctrl_config {
74     /*! Register base of IO Macro instance */
75     uintptr_t reg_base;
76 
77     /*! ECAM and MMIO memory map for x4_0 */
78     struct pcie_ecam_mmio_mmap x4_0_ecam_mmio_mmap;
79 
80     /*! ECAM and MMIO memory map for x4_1 */
81     struct pcie_ecam_mmio_mmap x4_1_ecam_mmio_mmap;
82 
83     /*! ECAM and MMIO memory map for x8 */
84     struct pcie_ecam_mmio_mmap x8_ecam_mmio_mmap;
85 
86     /*! ECAM and MMIO memory map for x16 */
87     struct pcie_ecam_mmio_mmap x16_ecam_mmio_mmap;
88 
89     /*! Identifier of the clock this module depends on */
90     fwk_id_t clock_id;
91 };
92 
93 /*!
94  * \}
95  */
96 
97 /*!
98  * \}
99  */
100 
101 #endif /* MOD_PCIE_INTEG_CTRL_H */
102