1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef MOD_SYSTEM_PLL_H
9 #define MOD_SYSTEM_PLL_H
10 
11 #include <fwk_element.h>
12 #include <fwk_macros.h>
13 
14 #include <stdbool.h>
15 #include <stdint.h>
16 
17 /*!
18  * \ingroup GroupModules Modules
19  * \defgroup GroupSystemPll System PLL Driver
20  *
21  * \details A driver for system PLL devices.
22  *
23  * \{
24  */
25 
26 /*! The slowest rate at which the PLL hardware can operate. */
27 #define MOD_SYSTEM_PLL_MIN_RATE (50UL * FWK_MHZ)
28 
29 /*! The fastest rate at which the PLL hardware can operate. */
30 #define MOD_SYSTEM_PLL_MAX_RATE (4UL * FWK_GHZ)
31 
32 /*! The maximum precision that can be used when setting the PLL rate. */
33 #define MOD_SYSTEM_PLL_MIN_INTERVAL (1UL * FWK_KHZ)
34 
35 /*! Indexes of APIs that the module offers for binding. */
36 enum mod_system_pll_api_types {
37     MOD_SYSTEM_PLL_API_TYPE_DEFAULT,
38     MOD_SYSTEM_PLL_API_COUNT,
39 };
40 
41 /*!
42  * \brief PLL device configuration.
43  */
44 struct mod_system_pll_dev_config {
45     /*! Pointer to the PLL's control register. */
46     volatile uint32_t * const control_reg;
47 
48     /*! Pointer to the PLL's status register, if any. */
49     volatile uint32_t * const status_reg;
50 
51     /*!
52      * Mask for the bit within the status register that indicates whether the
53      * PLL has locked at the programmed rate.
54      */
55     const uint32_t lock_flag_mask;
56 
57     /*! The initial rate the PLL is set to during initialization. */
58     const uint64_t initial_rate;
59 
60     /*!
61      * The slowest rate the PLL can be set to. This may be different from the
62      * hardware-imposed limit).
63      */
64     const uint64_t min_rate;
65 
66     /*!
67      * The fastest rate the PLL can be set to. This may be different from the
68      * hardware-imposed limit).
69      */
70     const uint64_t max_rate;
71 
72     /*!
73      * The maximum precision that can be used when setting the PLL rate. This
74      * may be different from the hardware-imposed limit).
75      */
76     const uint64_t min_step;
77 
78     /*!
79      * If \c true, the driver will not attempt to set a default frequency, or to
80      * otherwise configure the PLL during the pre-runtime phase. The PLL is
81      * expected to be initialized later in response to a notification or other
82      * event.
83      */
84     const bool defer_initialization;
85 };
86 
87 /*!
88  * \}
89  */
90 
91 #endif /* MOD_SYSTEM_PLL_H */
92