1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef FMW_CMSIS_H 9 #define FMW_CMSIS_H 10 11 #include <stdint.h> 12 13 #define __CHECK_DEVICE_DEFINES 14 #define __CM3_REV 0x0201U 15 #define __MPU_PRESENT 1U 16 #define __NVIC_PRIO_BITS 3U 17 #define __Vendor_SysTickConfig 0U 18 #define __VTOR_PRESENT 1U 19 20 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ 21 22 typedef enum IRQn { 23 Reset_IRQn = -15, 24 NonMaskableInt_IRQn = -14, 25 HardFault_IRQn = -13, 26 MemoryManagement_IRQn = -12, 27 BusFault_IRQn = -11, 28 UsageFault_IRQn = -10, 29 SVCall_IRQn = -5, 30 DebugMonitor_IRQn = -4, 31 PendSV_IRQn = -2, 32 SysTick_IRQn = -1, 33 34 WDOG_IRQ = 0, /* SCP System WatchDog (SP805) */ 35 TIM32KHZ_IRQ = 1, /* 32KHz Physical Timer */ 36 TIMREFCLK_IRQ = 2, /* REFCLK Physical Timer */ 37 MHU_HIGH_PRIO_IRQ = 3, /* MHU High Priority Non-Secure int. */ 38 MHU_LOW_PRIO_IRQ = 4, /* MHU Low Priority interrupt */ 39 MHU_SECURE_IRQ = 5, /* MHU Secure interrupt */ 40 CTI_TRIG_OUT_2_IRQ = 6, /* SCP CTI Trigger Interrupt */ 41 CTI_TRIG_OUT_3_IRQ = 7, /* SCP CTI Trigger Interrupt */ 42 CDBG_PWR_UP_REQ_IRQ = 8, /* Coresight Debug Power Request */ 43 CSYS_PWR_UP_REQ_IRQ = 9, /* Coresight System Power Request */ 44 CDBG_RST_REQ_IRQ = 10, /* Coresight Debug Reset Request */ 45 BIG_0_DBG_PWR_UP_IRQ = 11, /* big CPU0 Debug Power Up Request */ 46 BIG_1_DBG_PWR_UP_IRQ = 12, /* big CPU1 Debug Power Up Request */ 47 BIG_2_DBG_PWR_UP_IRQ = 13, /* big CPU2 Debug Power Up Request */ 48 BIG_3_DBG_PWR_UP_IRQ = 14, /* big CPU3 Debug Power Up Request */ 49 LITTLE_0_DBG_PWR_UP_IRQ = 15, /* LITTLE CPU0 Debug Power Up Request */ 50 LITTLE_1_DBG_PWR_UP_IRQ = 16, /* LITTLE CPU1 Debug Power Up Request */ 51 LITTLE_2_DBG_PWR_UP_IRQ = 17, /* LITTLE CPU2 Debug Power Up Request */ 52 LITTLE_3_DBG_PWR_UP_IRQ = 18, /* LITTLE CPU3 Debug Power Up Request */ 53 BIG_SAC_WAKEUP_REQ_IRQ = 19, /* big CPU Snoop Access Wakeup Request */ 54 LITTLE_SAC_WAKEUP_REQ_IRQ = 20, /* LITTLE CPU Snoop Access Wakeup Request */ 55 EXT_IF_WAKEUP_IRQ = 21, /* Extension Interface Access Wake-Up Request */ 56 EXT_IF_SERVICE_IRQ = 22, /* Extension Interface Access Service Request */ 57 EXT_IF_COHERENCY_IRQ = 23, /* Expansion Interface Coherency Req. */ 58 BIG_0_IRQ_WAKEUP_IRQ = 24, /* big CPU0 IRQ Wakeup Request */ 59 BIG_0_FIQ_WAKEUP_IRQ = 25, /* big CPU0 FIQ Wakeup Request */ 60 BIG_1_IRQ_WAKEUP_IRQ = 26, /* big CPU1 IRQ Wakeup Request */ 61 BIG_1_FIQ_WAKEUP_IRQ = 27, /* big CPU1 FIQ Wakeup Request */ 62 BIG_2_IRQ_WAKEUP_IRQ = 28, /* big CPU2 IRQ Wakeup Request */ 63 BIG_2_FIQ_WAKEUP_IRQ = 29, /* big CPU2 FIQ Wakeup Request */ 64 BIG_3_IRQ_WAKEUP_IRQ = 30, /* big CPU3 IRQ Wakeup Request */ 65 BIG_3_FIQ_WAKEUP_IRQ = 31, /* big CPU3 FIQ Wakeup Request */ 66 LITTLE_0_IRQ_WAKEUP_IRQ = 32, /* LITTLE CPU0 IRQ Wakeup Request */ 67 LITTLE_0_FIQ_WAKEUP_IRQ = 33, /* LITTLE CPU0 FIQ Wakeup Request */ 68 LITTLE_1_IRQ_WAKEUP_IRQ = 34, /* LITTLE CPU1 IRQ Wakeup Request */ 69 LITTLE_1_FIQ_WAKEUP_IRQ = 35, /* LITTLE CPU1 FIQ Wakeup Request */ 70 LITTLE_2_IRQ_WAKEUP_IRQ = 36, /* LITTLE CPU2 IRQ Wakeup Request */ 71 LITTLE_2_FIQ_WAKEUP_IRQ = 37, /* LITTLE CPU2 FIQ Wakeup Request */ 72 LITTLE_3_IRQ_WAKEUP_IRQ = 38, /* LITTLE CPU3 IRQ Wakeup Request */ 73 LITTLE_3_FIQ_WAKEUP_IRQ = 39, /* LITTLE CPU3 FIQ Wakeup Request */ 74 PPU_BIG_0_IRQ = 40, /* big CPU0 Power Policy Unit */ 75 PPU_BIG_1_IRQ = 41, /* big CPU1 Power Policy Unit */ 76 PPU_BIG_2_IRQ = 42, /* big CPU2 Power Policy Unit */ 77 PPU_BIG_3_IRQ = 43, /* big CPU3 Power Policy Unit */ 78 PPU_BIG_SSTOP_IRQ = 44, /* big SSTOP Power Policy Unit */ 79 PPU_LITTLE_0_IRQ = 45, /* LITTLE CPU0 Power Policy Unit */ 80 PPU_LITTLE_1_IRQ = 46, /* LITTLE CPU1 Power Policy Unit */ 81 PPU_LITTLE_2_IRQ = 47, /* LITTLE CPU2 Power Policy Unit */ 82 PPU_LITTLE_3_IRQ = 48, /* LITTLE CPU3 Power Policy Unit */ 83 PPU_LITTLE_SSTOP_IRQ = 49, /* LITTLE SSTOP Power Policy Unit */ 84 PPU_GPU_IRQ = 50, /* GPUTOP Sub-System Power Policy Unit */ 85 PPU_DBGSYS_IRQ = 51, /* Debug Sub-System Power Policy Unit */ 86 PPU_SYSTOP_IRQ = 52, /* SYSTOP Power Policy Unit */ 87 PLL_BIG_LOCK_IRQ = 53, /* big CPU PLL Lock */ 88 PLL_LITTLE_LOCK_IRQ = 54, /* LITTLE CPU PLL Lock */ 89 PLL_GPU_LOCK_IRQ = 55, /* GPU PLL Lock */ 90 PLL_SYS_LOCK_IRQ = 56, /* System PLL Lock */ 91 EXT_WAKEUP_IRQ = 57, /* External GIC Interrupt Wakeup */ 92 BIG_0_WARM_RST_REQ_IRQ = 58, /* big CPU0 Warm Reset Request */ 93 BIG_1_WARM_RST_REQ_IRQ = 59, /* big CPU1 Warm Reset Request */ 94 BIG_2_WARM_RST_REQ_IRQ = 60, /* big CPU2 Warm Reset Request */ 95 BIG_3_WARM_RST_REQ_IRQ = 61, /* big CPU3 Warm Reset Request */ 96 LITTLE_0_WARM_RST_REQ_IRQ = 62, /* LITTLE CPU0 Warm Reset Request */ 97 LITTLE_1_WARM_RST_REQ_IRQ = 63, /* LITTLE CPU1 Warm Reset Request */ 98 LITTLE_2_WARM_RST_REQ_IRQ = 64, /* LITTLE CPU2 Warm Reset Request */ 99 LITTLE_3_WARM_RST_REQ_IRQ = 65, /* LITTLE CPU3 Warm Reset Request */ 100 BIG_0_DBG_RST_REQ_IRQ = 66, /* big CPU0 Debug Reset Request */ 101 BIG_1_DBG_RST_REQ_IRQ = 67, /* big CPU1 Debug Reset Request */ 102 BIG_2_DBG_RST_REQ_IRQ = 68, /* big CPU2 Debug Reset Request */ 103 BIG_3_DBG_RST_REQ_IRQ = 69, /* big CPU3 Debug Reset Request */ 104 LITTLE_0_DBG_RST_REQ_IRQ = 70, /* LITTLE CPU0 Debug Reset Request */ 105 LITTLE_1_DBG_RST_REQ_IRQ = 71, /* LITTLE CPU1 Debug Reset Request */ 106 LITTLE_2_DBG_RST_REQ_IRQ = 72, /* LITTLE CPU2 Debug Reset Request */ 107 LITTLE_3_DBG_RST_REQ_IRQ = 73, /* LITTLE CPU3 Debug Reset Request */ 108 RESERVED74_IRQ = 74, /* Reserved */ 109 RESERVED75_IRQ = 75, /* Reserved */ 110 RESERVED76_IRQ = 76, /* Reserved */ 111 RESERVED77_IRQ = 77, /* Reserved */ 112 RESERVED78_IRQ = 78, /* Reserved */ 113 RESERVED79_IRQ = 79, /* Reserved */ 114 RESERVED80_IRQ = 80, /* Reserved */ 115 RESERVED81_IRQ = 81, /* Reserved */ 116 RESERVED82_IRQ = 82, /* Reserved */ 117 RESERVED83_IRQ = 83, /* Reserved */ 118 RESERVED84_IRQ = 84, /* Reserved */ 119 RESERVED85_IRQ = 85, /* Reserved */ 120 RESERVED86_IRQ = 86, /* Reserved */ 121 RESERVED87_IRQ = 87, /* Reserved */ 122 RESERVED88_IRQ = 88, /* Reserved */ 123 RESERVED89_IRQ = 89, /* Reserved */ 124 RESERVED90_IRQ = 90, /* Reserved */ 125 RESERVED91_IRQ = 91, /* Reserved */ 126 RESERVED92_IRQ = 92, /* Reserved */ 127 RESERVED93_IRQ = 93, /* Reserved */ 128 RESERVED94_IRQ = 94, /* Reserved */ 129 RESERVED95_IRQ = 95, /* Reserved */ 130 I2C_IRQ = 96, /* I2C Interrupt */ 131 LITTLE_PVT_IRQ = 97, /* LITTLE CPU PVT monitor Interrupt */ 132 BIG_PVT_IRQ = 98, /* big CPU PVT monitor Interrupt */ 133 GPU_PVT_IRQ = 99, /* GPU PVT monitor Interrupt */ 134 SOC_PVT_IRQ = 100, /* SoC PVT monitor Interrupt */ 135 SCP_EXT_INTR5_IRQ = 101, /* SCP Customer Extension */ 136 STD_CELL_PVT_IRQ = 102, /* Std Cell PVT monitor Interrupt */ 137 SCP_EXT_INTR7_IRQ = 103, /* SCP Customer Extension */ 138 PHY_TRAINING_IRQ = 104, /* PHY Training Interrupt */ 139 SCP_EXT_INTR9_IRQ = 105, /* SCP Customer Extension */ 140 SCP_EXT_INTR10_IRQ = 106, /* SCP Customer Extension */ 141 SCP_EXT_INTR11_IRQ = 107, /* SCP Customer Extension */ 142 SCP_EXT_INTR12_IRQ = 108, /* SCP Customer Extension */ 143 SCP_EXT_INTR13_IRQ = 109, /* SCP Customer Extension */ 144 SCP_EXT_INTR14_IRQ = 110, /* SCP Customer Extension */ 145 SCP_EXT_INTR15_IRQ = 111, /* SCP Customer Extension */ 146 SCP_EXT_INTR16_IRQ = 112, /* SCP Customer Extension */ 147 SCP_EXT_INTR17_IRQ = 113, /* SCP Customer Extension */ 148 SCP_EXT_INTR18_IRQ = 114, /* SCP Customer Extension */ 149 SCP_EXT_INTR19_IRQ = 115, /* SCP Customer Extension */ 150 SCP_EXT_INTR20_IRQ = 116, /* SCP Customer Extension */ 151 SCP_EXT_INTR21_IRQ = 117, /* SCP Customer Extension */ 152 SCP_EXT_INTR22_IRQ = 118, /* SCP Customer Extension */ 153 SCP_EXT_INTR23_IRQ = 119, /* SCP Customer Extension */ 154 SCP_EXT_INTR24_IRQ = 120, /* SCP Customer Extension */ 155 SCP_EXT_INTR25_IRQ = 121, /* SCP Customer Extension */ 156 SCP_EXT_INTR26_IRQ = 122, /* SCP Customer Extension */ 157 SCP_EXT_INTR27_IRQ = 123, /* SCP Customer Extension */ 158 SCP_EXT_INTR28_IRQ = 124, /* SCP Customer Extension */ 159 SCP_EXT_INTR29_IRQ = 125, /* SCP Customer Extension */ 160 SCP_EXT_INTR30_IRQ = 126, /* SCP Customer Extension */ 161 SCP_EXT_INTR31_IRQ = 127, /* SCP Customer Extension */ 162 163 IRQn_MAX = INT16_MAX, 164 } IRQn_Type; 165 166 #include <core_cm3.h> 167 168 #endif /* FMW_CMSIS_H */ 169