1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  *
7  * Description:
8  *     Juno Watchdog registers definition.
9  */
10 
11 #ifndef JUNO_WDOG_H
12 #define JUNO_WDOG_H
13 
14 #include "system_mmap.h"
15 
16 #include <fwk_macros.h>
17 
18 #include <stdint.h>
19 
20 struct sp805_reg {
21     FWK_RW  uint32_t    LOAD;
22     FWK_R   uint32_t    VALUE;
23     FWK_RW  uint32_t    CONTROL;
24     FWK_W   uint32_t    INTCLR;
25     FWK_R   uint32_t    RIS;
26     FWK_R   uint32_t    MIS;
27             uint8_t     RESERVED1[0xC00 - 0x18];
28     FWK_RW  uint32_t    LOCK;
29             uint8_t     RESERVED2[0xF00 - 0xC04];
30     FWK_RW  uint32_t    ITCR;
31     FWK_W   uint32_t    ITOP;
32             uint8_t     RESERVED3[0xFE0 - 0xF08];
33     FWK_R   uint32_t    PERIPHID0;
34     FWK_R   uint32_t    PERIPHID1;
35     FWK_R   uint32_t    PERIPHID2;
36     FWK_R   uint32_t    PERIPHID3;
37     FWK_R   uint32_t    PCELLID0;
38     FWK_R   uint32_t    PCELLID1;
39     FWK_R   uint32_t    PCELLID2;
40     FWK_R   uint32_t    PCELLID3;
41 };
42 
43 #define WDOG    ((struct sp805_reg *) WDOG_BASE)
44 
45 #define SP805_LOCK_EN_ACCESS            UINT32_C(0x1ACCE551)
46 #define SP805_CONTROL_INTR_EN           UINT32_C(0x00000001)
47 #define SP805_CONTROL_RESET_EN          UINT32_C(0x00000002)
48 
49 /* Watchdog frequency */
50 #define SCP_WDOG_FREQUENCY_KHZ          32
51 
52 /* Convert a period from milliseconds to watchdog timer ticks */
53 #define SCP_WDOG_MS_TO_TICKS(VALUE_MS)  ((VALUE_MS) * SCP_WDOG_FREQUENCY_KHZ)
54 
55 #endif /* JUNO_WDOG_H */
56